1 // SPDX-License-Identifier: GPL-2.0-or-later
5  *  -- christophe
14 #include <asm/code-patching.h>
34 		return p + va - VIRT_IMMR_BASE;  in v_block_mapped()
51 		return VIRT_IMMR_BASE + pa - p;  in p_block_mapped()
80 		return -EINVAL;  in __early_map_kernel_hugepage()
84 			return -EINVAL;  in __early_map_kernel_hugepage()
98 		return -ENOMEM;  in __early_map_kernel_hugepage()
102 		return -EINVAL;  in __early_map_kernel_hugepage()
110  * MMU_init_hw does the chip-specific initialization of the MMU hardware.
129 static void mmu_mapin_ram_chunk(unsigned long offset, unsigned long top,  in mmu_mapin_ram_chunk()  argument
135 	WARN_ON(!IS_ALIGNED(offset, SZ_512K) || !IS_ALIGNED(top, SZ_512K));  in mmu_mapin_ram_chunk()
137 	for (; p < ALIGN(p, SZ_8M) && p < top; p += SZ_512K, v += SZ_512K)  in mmu_mapin_ram_chunk()
139 	for (; p < ALIGN_DOWN(top, SZ_8M) && p < top; p += SZ_8M, v += SZ_8M)  in mmu_mapin_ram_chunk()
141 	for (; p < ALIGN_DOWN(top, SZ_512K) && p < top; p += SZ_512K, v += SZ_512K)  in mmu_mapin_ram_chunk()
145 		flush_tlb_kernel_range(PAGE_OFFSET + v, PAGE_OFFSET + top);  in mmu_mapin_ram_chunk()
148 unsigned long __init mmu_mapin_ram(unsigned long base, unsigned long top)  in mmu_mapin_ram()  argument
156 	WARN_ON(top < einittext8);  in mmu_mapin_ram()
165 		top = boundary;  in mmu_mapin_ram()
168 		mmu_mapin_ram_chunk(einittext8, top, PAGE_KERNEL, true);  in mmu_mapin_ram()
171 	if (top > SZ_32M)  in mmu_mapin_ram()
172 		memblock_set_current_limit(top);  in mmu_mapin_ram()
174 	block_mapped_ram = top;  in mmu_mapin_ram()
176 	return top;  in mmu_mapin_ram()
234 	/* Register M_TWB will contain base address of level 1 table minus the  in set_context()
236 	 * level 1 table are done relative to lower part of kernel PGDIR base  in set_context()
239 	mtspr(SPRN_M_TWB, __pa(pgd) - offset);  in set_context()
242 	mtspr(SPRN_M_CASID, id - 1);  in set_context()