mm/nohash/44x.c

1 // SPDX-License-Identifier: GPL-2.0-or-later
8  *  -- paulus
11  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
27 #include <asm/code-patching.h>
31 /* Used by the 44x TLB replacement exception handler.
35 unsigned int tlb_44x_hwater = PPC44x_TLB_SIZE - 1 - PPC44x_EARLY_TLBS;
42 	/* The TLB miss handlers hard codes the watermark in a cmpli  in ppc44x_update_tlb_hwater()
45 	 * in the 2 TLB miss handlers when updating the value  in ppc44x_update_tlb_hwater()
52  * "Pins" a 256MB TLB entry in AS0 for kernel lowmem for 44x type MMU
56 	unsigned int entry = tlb_44x_hwater--;  in ppc44x_pin_tlb()
71 	  "i" (PPC44x_TLB_PAGEID),  in ppc44x_pin_tlb()
72 	  "i" (PPC44x_TLB_XLAT),  in ppc44x_pin_tlb()
73 	  "i" (PPC44x_TLB_ATTRIB));  in ppc44x_pin_tlb()
93 	return -1;  in ppc47x_find_free_bolted()
122  * "Pins" a 256MB TLB entry in AS0 for kernel lowmem for 47x type MMU
139 	pr_debug("256M TLB entry for 0x%08x->0x%08x in bolt slot %d\n",  in ppc47x_pin_tlb()
171 	unsigned long memstart = memstart_addr & ~(PPC_PIN_SIZE - 1);  in mmu_mapin_ram()
187 			int i;  in mmu_mapin_ram()  local
190 			for (i = 0; i < 255; i++) {  in mmu_mapin_ram()
191 				if (test_bit(i, tlb_47x_boltmap))  in mmu_mapin_ram()
192 					printk("%d ", i);  in mmu_mapin_ram()
204 	u64 size;  in setup_initial_memory_limit()  local
213 	/* 44x has a 256M TLB entry pinned at boot */  in setup_initial_memory_limit()
214 	size = (min_t(u64, first_memblock_size, PPC_PIN_SIZE));  in setup_initial_memory_limit()
215 	memblock_set_current_limit(first_memblock_base + size);  in setup_initial_memory_limit()
222 	unsigned long memstart = memstart_addr & ~(PPC_PIN_SIZE - 1);  in mmu_init_secondary()
228 	 * linear mapping in the TLB and we can't take faults yet  in mmu_init_secondary()