Lines Matching +full:0 +full:x1234
19 #define IGNORE_GPR(n) (0x1UL << (n))
20 #define IGNORE_XER (0x1UL << 32)
21 #define IGNORE_CCR (0x1UL << 33)
22 #define NEGATIVE_TEST (0x1UL << 63)
62 memset(regs, 0, sizeof(struct pt_regs)); in init_pt_regs()
69 asm volatile("mfmsr %0" : "=r"(regs->msr)); in init_pt_regs()
93 unsigned long a = 0x23; in test_ld()
99 /* ld r5, 0(r3) */ in test_ld()
100 stepped = emulate_step(®s, ppc_inst(PPC_RAW_LD(5, 3, 0))); in test_ld()
111 unsigned long a = 0x23; in test_pld()
122 /* pld r5, 0(r3), 0 */ in test_pld()
123 stepped = emulate_step(®s, TEST_PLD(5, 3, 0, 0)); in test_pld()
134 unsigned int a = 0x4545; in test_lwz()
140 /* lwz r5, 0(r3) */ in test_lwz()
141 stepped = emulate_step(®s, ppc_inst(PPC_RAW_LWZ(5, 3, 0))); in test_lwz()
152 unsigned int a = 0x4545; in test_plwz()
163 /* plwz r5, 0(r3), 0 */ in test_plwz()
165 stepped = emulate_step(®s, TEST_PLWZ(5, 3, 0, 0)); in test_plwz()
176 unsigned int a[3] = {0x0, 0x0, 0x1234}; in test_lwzx()
182 regs.gpr[5] = 0x8765; in test_lwzx()
195 unsigned long a = 0x1234; in test_std()
200 regs.gpr[5] = 0x5678; in test_std()
202 /* std r5, 0(r3) */ in test_std()
203 stepped = emulate_step(®s, ppc_inst(PPC_RAW_STD(5, 3, 0))); in test_std()
213 unsigned long a = 0x1234; in test_pstd()
223 regs.gpr[5] = 0x5678; in test_pstd()
225 /* pstd r5, 0(r3), 0 */ in test_pstd()
226 stepped = emulate_step(®s, TEST_PSTD(5, 3, 0, 0)); in test_pstd()
236 unsigned long a = 0x1234; in test_ldarx_stdcx()
238 unsigned long cr0_eq = 0x1 << 29; /* eq bit of CR0 */ in test_ldarx_stdcx()
241 asm volatile("mfcr %0" : "=r"(regs.ccr)); in test_ldarx_stdcx()
247 regs.gpr[4] = 0; in test_ldarx_stdcx()
248 regs.gpr[5] = 0x5678; in test_ldarx_stdcx()
250 /* ldarx r5, r3, r4, 0 */ in test_ldarx_stdcx()
251 stepped = emulate_step(®s, ppc_inst(PPC_RAW_LDARX(5, 3, 4, 0))); in test_ldarx_stdcx()
258 if (stepped <= 0 || regs.gpr[5] != 0x1234) { in test_ldarx_stdcx()
266 regs.gpr[5] = 0x9ABC; in test_ldarx_stdcx()
277 * In this case cr0.eq bit will be set to 0. in test_ldarx_stdcx()
306 regs.gpr[4] = 0; in test_lfsx_stfsx()
355 /* plfs frt10, 0(r3), 0 */ in test_plfs_pstfs()
356 stepped = emulate_step(®s, TEST_PLFS(10, 3, 0, 0)); in test_plfs_pstfs()
368 /* pstfs frs10, 0(r3), 0 */ in test_plfs_pstfs()
369 stepped = emulate_step(®s, TEST_PSTFS(10, 3, 0, 0)); in test_plfs_pstfs()
396 regs.gpr[4] = 0; in test_lfdx_stfdx()
445 /* plfd frt10, 0(r3), 0 */ in test_plfd_pstfd()
446 stepped = emulate_step(®s, TEST_PLFD(10, 3, 0, 0)); in test_plfd_pstfd()
458 /* pstfd frs10, 0(r3), 0 */ in test_plfd_pstfd()
459 stepped = emulate_step(®s, TEST_PSTFD(10, 3, 0, 0)); in test_plfd_pstfd()
508 cached_b[0] = c.b[0] = 923745; in test_lvx_stvx()
514 regs.gpr[4] = 0; in test_lvx_stvx()
527 c.b[0] = 4987513; in test_lvx_stvx()
535 if (stepped == 1 && cached_b[0] == c.b[0] && cached_b[1] == c.b[1] && in test_lvx_stvx()
565 cached_b[0] = c.b[0] = 18233; in test_lxvd2x_stxvd2x()
571 regs.gpr[4] = 0; in test_lxvd2x_stxvd2x()
588 c.b[0] = 21379463; in test_lxvd2x_stxvd2x()
596 if (stepped == 1 && cached_b[0] == c.b[0] && cached_b[1] == c.b[1] && in test_lxvd2x_stxvd2x()
657 .gpr[0] = LONG_MAX,
698 .descr = "RA = ULONG_MAX, RB = 0x1",
702 .gpr[22] = 0x1,
738 .descr = "RA = UINT_MAX, RB = 0x1",
742 .gpr[22] = 0x1,
785 .descr = "RA = ULONG_MAX, RB = 0x1",
789 .gpr[22] = 0x1,
825 .descr = "RA = UINT_MAX, RB = 0x1",
829 .gpr[22] = 0x1,
870 .descr = "RA = ULONG_MAX, RB = 0x1",
874 .gpr[22] = 0x1,
910 .descr = "RA = UINT_MAX, RB = 0x1",
914 .gpr[22] = 0x1,
965 .descr = "RA = ULONG_MAX, RB = 0x1",
969 .gpr[22] = 0x1,
1005 .descr = "RA = UINT_MAX, RB = 0x1",
1009 .gpr[22] = 0x1,
1034 .descr = "RA = 1L, RB = 0",
1039 .gpr[22] = 0,
1064 .descr = "RA = 1L, RB = 0",
1069 .gpr[22] = 0,
1095 .descr = "RA = 1L, RB = 0",
1100 .gpr[22] = 0,
1143 .descr = "RA = 1L, RB = 0",
1148 .gpr[22] = 0,
1183 .descr = "RA = LONG_MIN, SI = SI_MIN, R = 0",
1184 .instr = TEST_PADDI(21, 22, SI_MIN, 0),
1186 .gpr[21] = 0,
1191 .descr = "RA = LONG_MIN, SI = SI_MAX, R = 0",
1192 .instr = TEST_PADDI(21, 22, SI_MAX, 0),
1194 .gpr[21] = 0,
1199 .descr = "RA = LONG_MAX, SI = SI_MAX, R = 0",
1200 .instr = TEST_PADDI(21, 22, SI_MAX, 0),
1202 .gpr[21] = 0,
1207 .descr = "RA = ULONG_MAX, SI = SI_UMAX, R = 0",
1208 .instr = TEST_PADDI(21, 22, SI_UMAX, 0),
1210 .gpr[21] = 0,
1215 .descr = "RA = ULONG_MAX, SI = 0x1, R = 0",
1216 .instr = TEST_PADDI(21, 22, 0x1, 0),
1218 .gpr[21] = 0,
1223 .descr = "RA = INT_MIN, SI = SI_MIN, R = 0",
1224 .instr = TEST_PADDI(21, 22, SI_MIN, 0),
1226 .gpr[21] = 0,
1231 .descr = "RA = INT_MIN, SI = SI_MAX, R = 0",
1232 .instr = TEST_PADDI(21, 22, SI_MAX, 0),
1234 .gpr[21] = 0,
1239 .descr = "RA = INT_MAX, SI = SI_MAX, R = 0",
1240 .instr = TEST_PADDI(21, 22, SI_MAX, 0),
1242 .gpr[21] = 0,
1247 .descr = "RA = UINT_MAX, SI = 0x1, R = 0",
1248 .instr = TEST_PADDI(21, 22, 0x1, 0),
1250 .gpr[21] = 0,
1255 .descr = "RA = UINT_MAX, SI = SI_MAX, R = 0",
1256 .instr = TEST_PADDI(21, 22, SI_MAX, 0),
1258 .gpr[21] = 0,
1263 .descr = "RA is r0, SI = SI_MIN, R = 0",
1264 .instr = TEST_PADDI(21, 0, SI_MIN, 0),
1266 .gpr[21] = 0x0,
1270 .descr = "RA = 0, SI = SI_MIN, R = 0",
1271 .instr = TEST_PADDI(21, 22, SI_MIN, 0),
1273 .gpr[21] = 0x0,
1274 .gpr[22] = 0x0,
1278 .descr = "RA is r0, SI = 0, R = 1",
1279 .instr = TEST_PADDI(21, 0, 0, 1),
1281 .gpr[21] = 0,
1286 .instr = TEST_PADDI(21, 0, SI_MIN, 1),
1288 .gpr[21] = 0,
1291 /* Invalid instruction form with R = 1 and RA != 0 */
1293 .descr = "RA = R22(0), SI = 0, R = 1",
1294 .instr = TEST_PADDI(21, 22, 0, 1),
1297 .gpr[21] = 0,
1298 .gpr[22] = 0,
1328 return 0; in emulate_compute_instr()
1346 return 0; in execute_compute_instr()
1350 pr_info("GPR%u mismatch, exp = 0x%016lx, got = 0x%016lx\n", \
1354 pr_info("%s mismatch, exp = 0x%016lx, got = 0x%016lx\n", \
1366 for (i = 0; i < ARRAY_SIZE(compute_tests); i++) { in run_tests_compute()
1374 for (j = 0; j < MAX_SUBTESTS && test->subtests[j].descr; j++) { in run_tests_compute()
1393 rc = emulate_compute_instr(&got, instr, negative) != 0; in run_tests_compute()
1404 for (k = 0; k < 32; k++) { in run_tests_compute()
1444 return 0; in test_emulate_step()