include/asm/reg_booke.h

70 #define SPRN_IAC3	0x13A	/* Instruction Address Compare 3 */
71 #define SPRN_IAC4	0x13B	/* Instruction Address Compare 4 */
72 #define SPRN_DVC1	0x13E	/* Data Value Compare Register 1 */
73 #define SPRN_DVC2	0x13F	/* Data Value Compare Register 2 */
170 #define SPRN_DCMP	0x3D1	/* Data TLB Compare Register */
198 #define SPRN_IAC1	0x138	/* Instruction Address Compare 1 */
199 #define SPRN_IAC2	0x139	/* Instruction Address Compare 2 */
200 #define SPRN_DAC1	0x13C	/* Data Address Compare 1 */
201 #define SPRN_DAC2	0x13D	/* Data Address Compare 2 */
215 #define SPRN_DAC1	0x3F6	/* Data Address Compare 1 */
216 #define SPRN_DAC2	0x3F7	/* Data Address Compare 2 */
321 #define DBSR_IAC1	0x00800000	/* Instr Address Compare 1 Event */
322 #define DBSR_IAC2	0x00400000	/* Instr Address Compare 2 Event */
323 #define DBSR_IAC3	0x00200000	/* Instr Address Compare 3 Event */
324 #define DBSR_IAC4	0x00100000	/* Instr Address Compare 4 Event */
325 #define DBSR_DAC1R	0x00080000	/* Data Addr Compare 1 Read Event */
326 #define DBSR_DAC1W	0x00040000	/* Data Addr Compare 1 Write Event */
327 #define DBSR_DAC2R	0x00020000	/* Data Addr Compare 2 Read Event */
328 #define DBSR_DAC2W	0x00010000	/* Data Addr Compare 2 Write Event */
332 #define DBSR_IAC12ATS	0x00000002	/* Instr Address Compare 1/2 Toggle */
333 #define DBSR_IAC34ATS	0x00000001	/* Instr Address Compare 3/4 Toggle */
340 #define DBSR_IAC1	0x04000000	/* Instruction Address Compare 1 Event */
341 #define DBSR_IAC2	0x02000000	/* Instruction Address Compare 2 Event */
342 #define DBSR_IAC3	0x00080000	/* Instruction Address Compare 3 Event */
343 #define DBSR_IAC4	0x00040000	/* Instruction Address Compare 4 Event */
344 #define DBSR_DAC1R	0x01000000	/* Data Address Compare 1 Read Event */
345 #define DBSR_DAC1W	0x00800000	/* Data Address Compare 1 Write Event */
346 #define DBSR_DAC2R	0x00400000	/* Data Address Compare 2 Read Event */
347 #define DBSR_DAC2W	0x00200000	/* Data Address Compare 2 Write Event */
385 #define DBCR0_IA1	0x00800000	/* Instr Addr compare 1 enable */
387 #define DBCR0_IA2	0x00400000	/* Instr Addr compare 2 enable */
391 #define DBCR0_IA3	0x00080000	/* Instr Addr compare 3 enable */
393 #define DBCR0_IA4	0x00040000	/* Instr Addr compare 4 enable */
448 #define DBCR0_IAC1	0x00800000	/* Instr Addr compare 1 enable */
449 #define DBCR0_IAC2	0x00400000	/* Instr Addr compare 2 enable */
450 #define DBCR0_IAC3	0x00200000	/* Instr Addr compare 3 enable */
451 #define DBCR0_IAC4	0x00100000	/* Instr Addr compare 4 enable */