Lines Matching +full:0 +full:x10080000
50 #define MSR_FE0_LG 11 /* Floating Exception mode 0 */
55 #define MSR_IP_LG 6 /* Exception prefix 0x000/0xFFF */
62 #define MSR_LE_LG 0 /* Little Endian */
77 #define MSR_SF 0
78 #define MSR_ISF 0
79 #define MSR_HV 0
80 #define MSR_S 0
88 #define MSR_SPE 0
102 #define MSR_FE0 __MASK(MSR_FE0_LG) /* Floating Exception mode 0 */
107 #define MSR_IP __MASK(MSR_IP_LG) /* Exception prefix 0x000/0xFFF */
119 #define MSR_TS_N 0 /* Non-transactional */
128 #define MSR_TM_ACTIVE(x) (((x) & MSR_TS_MASK) != 0) /* Transaction active? */
130 #define MSR_TM_ACTIVE(x) 0
155 #define MSR_64BIT 0
160 #define CR0_MASK 0xF
161 #define CR0_TBEGIN_FAILURE (0x2 << 28) /* 0b0010 */
165 #define PSSCR_RL_MASK 0x0000000F /* Requested Level */
166 #define PSSCR_MTL_MASK 0x000000F0 /* Maximum Transition Level */
167 #define PSSCR_TR_MASK 0x00000300 /* Transition State */
168 #define PSSCR_PSLL_MASK 0x000F0000 /* Power-Saving Level Limit */
169 #define PSSCR_EC 0x00100000 /* Exit Criterion */
170 #define PSSCR_ESL 0x00200000 /* Enable State Loss */
171 #define PSSCR_SD 0x00400000 /* Status Disable */
172 #define PSSCR_PLS 0xf000000000000000 /* Power-saving Level Status */
174 #define PSSCR_GUEST_VIS 0xf0000000000003ffUL /* Guest-visible PSSCR fields */
175 #define PSSCR_FAKE_SUSPEND 0x00000400 /* Fake-suspend bit (P9 DD2.2) */
179 #define FPSCR_FX 0x80000000 /* FPU exception summary */
180 #define FPSCR_FEX 0x40000000 /* FPU enabled exception summary */
181 #define FPSCR_VX 0x20000000 /* Invalid operation summary */
182 #define FPSCR_OX 0x10000000 /* Overflow exception summary */
183 #define FPSCR_UX 0x08000000 /* Underflow exception summary */
184 #define FPSCR_ZX 0x04000000 /* Zero-divide exception summary */
185 #define FPSCR_XX 0x02000000 /* Inexact exception summary */
186 #define FPSCR_VXSNAN 0x01000000 /* Invalid op for SNaN */
187 #define FPSCR_VXISI 0x00800000 /* Invalid op for Inv - Inv */
188 #define FPSCR_VXIDI 0x00400000 /* Invalid op for Inv / Inv */
189 #define FPSCR_VXZDZ 0x00200000 /* Invalid op for Zero / Zero */
190 #define FPSCR_VXIMZ 0x00100000 /* Invalid op for Inv * Zero */
191 #define FPSCR_VXVC 0x00080000 /* Invalid op for Compare */
192 #define FPSCR_FR 0x00040000 /* Fraction rounded */
193 #define FPSCR_FI 0x00020000 /* Fraction inexact */
194 #define FPSCR_FPRF 0x0001f000 /* FPU Result Flags */
195 #define FPSCR_FPCC 0x0000f000 /* FPU Condition Codes */
196 #define FPSCR_VXSOFT 0x00000400 /* Invalid op for software request */
197 #define FPSCR_VXSQRT 0x00000200 /* Invalid op for square root */
198 #define FPSCR_VXCVI 0x00000100 /* Invalid op for integer convert */
199 #define FPSCR_VE 0x00000080 /* Invalid op exception enable */
200 #define FPSCR_OE 0x00000040 /* IEEE overflow exception enable */
201 #define FPSCR_UE 0x00000020 /* IEEE underflow exception enable */
202 #define FPSCR_ZE 0x00000010 /* IEEE zero divide exception enable */
203 #define FPSCR_XE 0x00000008 /* FP inexact exception enable */
204 #define FPSCR_NI 0x00000004 /* FPU non IEEE-Mode */
205 #define FPSCR_RN 0x00000003 /* FPU rounding control */
208 #define SPEFSCR_SOVH 0x80000000 /* Summary integer overflow high */
209 #define SPEFSCR_OVH 0x40000000 /* Integer overflow high */
210 #define SPEFSCR_FGH 0x20000000 /* Embedded FP guard bit high */
211 #define SPEFSCR_FXH 0x10000000 /* Embedded FP sticky bit high */
212 #define SPEFSCR_FINVH 0x08000000 /* Embedded FP invalid operation high */
213 #define SPEFSCR_FDBZH 0x04000000 /* Embedded FP div by zero high */
214 #define SPEFSCR_FUNFH 0x02000000 /* Embedded FP underflow high */
215 #define SPEFSCR_FOVFH 0x01000000 /* Embedded FP overflow high */
216 #define SPEFSCR_FINXS 0x00200000 /* Embedded FP inexact sticky */
217 #define SPEFSCR_FINVS 0x00100000 /* Embedded FP invalid op. sticky */
218 #define SPEFSCR_FDBZS 0x00080000 /* Embedded FP div by zero sticky */
219 #define SPEFSCR_FUNFS 0x00040000 /* Embedded FP underflow sticky */
220 #define SPEFSCR_FOVFS 0x00020000 /* Embedded FP overflow sticky */
221 #define SPEFSCR_MODE 0x00010000 /* Embedded FP mode */
222 #define SPEFSCR_SOV 0x00008000 /* Integer summary overflow */
223 #define SPEFSCR_OV 0x00004000 /* Integer overflow */
224 #define SPEFSCR_FG 0x00002000 /* Embedded FP guard bit */
225 #define SPEFSCR_FX 0x00001000 /* Embedded FP sticky bit */
226 #define SPEFSCR_FINV 0x00000800 /* Embedded FP invalid operation */
227 #define SPEFSCR_FDBZ 0x00000400 /* Embedded FP div by zero */
228 #define SPEFSCR_FUNF 0x00000200 /* Embedded FP underflow */
229 #define SPEFSCR_FOVF 0x00000100 /* Embedded FP overflow */
230 #define SPEFSCR_FINXE 0x00000040 /* Embedded FP inexact enable */
231 #define SPEFSCR_FINVE 0x00000020 /* Embedded FP invalid op. enable */
232 #define SPEFSCR_FDBZE 0x00000010 /* Embedded FP div by zero enable */
233 #define SPEFSCR_FUNFE 0x00000008 /* Embedded FP underflow enable */
234 #define SPEFSCR_FOVFE 0x00000004 /* Embedded FP overflow enable */
235 #define SPEFSCR_FRMC 0x00000003 /* Embedded FP rounding mode control */
240 #define SPRN_PID 0x3B1 /* Process ID */
242 #define SPRN_PID 0x030 /* Process ID */
244 #define SPRN_PID0 SPRN_PID/* Process ID Register 0 */
248 #define SPRN_CTR 0x009 /* Count Register */
249 #define SPRN_DSCR 0x11
250 #define SPRN_CFAR 0x1c /* Come From Address Register */
251 #define SPRN_AMR 0x1d /* Authority Mask Register */
252 #define SPRN_UAMOR 0x9d /* User Authority Mask Override Register */
253 #define SPRN_AMOR 0x15d /* Authority Mask Override Register */
254 #define SPRN_ACOP 0x1F /* Available Coprocessor Register */
255 #define SPRN_TFIAR 0x81 /* Transaction Failure Inst Addr */
256 #define SPRN_TEXASR 0x82 /* Transaction EXception & Summary */
257 #define SPRN_TEXASRU 0x83 /* '' '' '' Upper 32 */
275 #define TEXASR_FC (ASM_CONST(0xFF) << TEXASR_FC_LG)
277 #define SPRN_TFHAR 0x80 /* Transaction Failure Handler Addr */
280 #define SPRN_CTRLF 0x088
281 #define SPRN_CTRLT 0x098
282 #define CTRL_CT 0xc0000000 /* current thread */
283 #define CTRL_CT0 0x80000000 /* thread 0 */
284 #define CTRL_CT1 0x40000000 /* thread 1 */
285 #define CTRL_TE 0x00c00000 /* thread enable */
286 #define CTRL_RUNLATCH 0x1
287 #define SPRN_DAWR0 0xB4
288 #define SPRN_DAWR1 0xB5
289 #define SPRN_RPR 0xBA /* Relative Priority Register */
290 #define SPRN_CIABR 0xBB
291 #define CIABR_PRIV 0x3
295 #define SPRN_DAWRX0 0xBC
296 #define SPRN_DAWRX1 0xBD
297 #define DAWRX_USER __MASK(0)
304 #define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */
305 #define SPRN_DABR2 0x13D /* e300 */
306 #define SPRN_DABRX 0x3F7 /* Data Address Breakpoint Register Extension */
307 #define DABRX_USER __MASK(0)
312 #define SPRN_DAR 0x013 /* Data Address Register */
313 #define SPRN_DBCR 0x136 /* e300 Data Breakpoint Control Reg */
314 #define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */
315 #define DSISR_BAD_DIRECT_ST 0x80000000 /* Obsolete: Direct store error */
316 #define DSISR_NOHPTE 0x40000000 /* no translation found */
317 #define DSISR_ATTR_CONFLICT 0x20000000 /* P9: Process vs. Partition attr */
318 #define DSISR_NOEXEC_OR_G 0x10000000 /* Alias of SRR1 bit, see below */
319 #define DSISR_PROTFAULT 0x08000000 /* protection fault */
320 #define DSISR_BADACCESS 0x04000000 /* bad access to CI or G */
321 #define DSISR_ISSTORE 0x02000000 /* access was a store */
322 #define DSISR_DABRMATCH 0x00400000 /* hit data breakpoint */
323 #define DSISR_NOSEGMENT 0x00200000 /* STAB miss (unsupported) */
324 #define DSISR_KEYFAULT 0x00200000 /* Storage Key fault */
325 #define DSISR_BAD_EXT_CTRL 0x00100000 /* Obsolete: External ctrl error */
326 #define DSISR_UNSUPP_MMU 0x00080000 /* P9: Unsupported MMU config */
327 #define DSISR_SET_RC 0x00040000 /* P9: Failed setting of R/C bits */
328 #define DSISR_PRTABLE_FAULT 0x00020000 /* P9: Fault on process table */
329 #define DSISR_ICSWX_NO_CT 0x00004000 /* P7: icswx unavailable cp type */
330 #define DSISR_BAD_COPYPASTE 0x00000008 /* P9: Copy/Paste on wrong memtype */
331 #define DSISR_BAD_AMO 0x00000004 /* P9: Incorrect AMO opcode */
332 #define DSISR_BAD_CI_LDST 0x00000002 /* P8: Bad HV CI load/store */
336 * 0 on DSIs. However, on ISIs, the corresponding bit in SRR1
361 * These bits are equivalent in SRR1 and DSISR for 0x400
373 #define SPRN_TBRL 0x10C /* Time Base Read Lower Register (user, R/O) */
374 #define SPRN_TBRU 0x10D /* Time Base Read Upper Register (user, R/O) */
375 #define SPRN_CIR 0x11B /* Chip Information Register (hyper, R/0) */
376 #define SPRN_TBWL 0x11C /* Time Base Lower Register (super, R/W) */
377 #define SPRN_TBWU 0x11D /* Time Base Upper Register (super, R/W) */
378 #define SPRN_TBU40 0x11E /* Timebase upper 40 bits (hyper, R/W) */
379 #define SPRN_SPURR 0x134 /* Scaled PURR */
380 #define SPRN_HSPRG0 0x130 /* Hypervisor Scratch 0 */
381 #define SPRN_HSPRG1 0x131 /* Hypervisor Scratch 1 */
382 #define SPRN_HDSISR 0x132
383 #define SPRN_HDAR 0x133
384 #define SPRN_HDEC 0x136 /* Hypervisor Decrementer */
385 #define SPRN_HIOR 0x137 /* 970 Hypervisor interrupt offset */
386 #define SPRN_RMOR 0x138 /* Real mode offset register */
387 #define SPRN_HRMOR 0x139 /* Real mode offset register */
388 #define SPRN_HSRR0 0x13A /* Hypervisor Save/Restore 0 */
389 #define SPRN_HSRR1 0x13B /* Hypervisor Save/Restore 1 */
390 #define SPRN_ASDR 0x330 /* Access segment descriptor register */
391 #define SPRN_IC 0x350 /* Virtual Instruction Count */
392 #define SPRN_VTB 0x351 /* Virtual Time Base */
393 #define SPRN_LDBAR 0x352 /* LD Base Address Register */
394 #define SPRN_PMICR 0x354 /* Power Management Idle Control Reg */
395 #define SPRN_PMSR 0x355 /* Power Management Status Reg */
396 #define SPRN_PMMAR 0x356 /* Power Management Memory Activity Register */
397 #define SPRN_PSSCR 0x357 /* Processor Stop Status and Control Register (ISA 3.0) */
398 #define SPRN_PSSCR_PR 0x337 /* PSSCR ISA 3.0, privileged mode access */
399 #define SPRN_PMCR 0x374 /* Power Management Control Register */
400 #define SPRN_RWMR 0x375 /* Region-Weighting Mode Register */
413 #define FSCR_FP_LG 0 /* Enable Floating Point */
414 #define SPRN_FSCR 0x099 /* Facility Status & Control Register */
420 #define SPRN_HFSCR 0xbe /* HV=1 Facility Status & Control Register */
431 #define HFSCR_INTR_CAUSE (ASM_CONST(0xFF) << 56) /* interrupt cause */
432 #define SPRN_TAR 0x32f /* Target Address Register */
433 #define SPRN_LPCR 0x13E /* LPAR Control Register */
434 #define LPCR_VPM0 ASM_CONST(0x8000000000000000)
435 #define LPCR_VPM1 ASM_CONST(0x4000000000000000)
436 #define LPCR_ISL ASM_CONST(0x2000000000000000)
441 #define LPCR_VRMASD (ASM_CONST(0x1f) << LPCR_VRMASD_SH)
442 #define LPCR_VRMA_L ASM_CONST(0x0008000000000000)
443 #define LPCR_VRMA_LP0 ASM_CONST(0x0001000000000000)
444 #define LPCR_VRMA_LP1 ASM_CONST(0x0000800000000000)
445 #define LPCR_RMLS 0x1C000000 /* Implementation dependent RMO limit sel */
447 #define LPCR_ILE ASM_CONST(0x0000000002000000) /* !HV irqs set MSR:LE */
448 #define LPCR_AIL ASM_CONST(0x0000000001800000) /* Alternate interrupt location */
449 #define LPCR_AIL_0 ASM_CONST(0x0000000000000000) /* MMU off exception offset 0x0 */
450 #define LPCR_AIL_3 ASM_CONST(0x0000000001800000) /* MMU on exception offset 0xc00...4xxx */
451 #define LPCR_ONL ASM_CONST(0x0000000000040000) /* online - PURR/SPURR count */
452 #define LPCR_LD ASM_CONST(0x0000000000020000) /* large decremeter */
453 #define LPCR_PECE ASM_CONST(0x000000000001f000) /* powersave exit cause enable */
454 #define LPCR_PECEDP ASM_CONST(0x0000000000010000) /* directed priv dbells cause exit */
455 #define LPCR_PECEDH ASM_CONST(0x0000000000008000) /* directed hyp dbells cause exit */
456 #define LPCR_PECE0 ASM_CONST(0x0000000000004000) /* ext. exceptions can cause exit */
457 #define LPCR_PECE1 ASM_CONST(0x0000000000002000) /* decrementer can cause exit */
458 #define LPCR_PECE2 ASM_CONST(0x0000000000001000) /* machine check etc can cause exit */
459 #define LPCR_PECE_HVEE ASM_CONST(0x0000400000000000) /* P9 Wakeup on HV interrupts */
460 #define LPCR_MER ASM_CONST(0x0000000000000800) /* Mediated External Exception */
462 #define LPCR_GTSE ASM_CONST(0x0000000000000400) /* Guest Translation Shootdown Enable */
463 #define LPCR_TC ASM_CONST(0x0000000000000200) /* Translation control */
464 #define LPCR_HEIC ASM_CONST(0x0000000000000010) /* Hypervisor External Interrupt Control */
465 #define LPCR_LPES 0x0000000c
466 #define LPCR_LPES0 ASM_CONST(0x0000000000000008) /* LPAR Env selector 0 */
467 #define LPCR_LPES1 ASM_CONST(0x0000000000000004) /* LPAR Env selector 1 */
469 #define LPCR_RMI ASM_CONST(0x0000000000000002) /* real mode is cache inhibit */
470 #define LPCR_HVICE ASM_CONST(0x0000000000000002) /* P9: HV interrupt enable */
471 #define LPCR_HDICE ASM_CONST(0x0000000000000001) /* Hyp Decr enable (HV,PR,EE) */
472 #define LPCR_UPRT ASM_CONST(0x0000000000400000) /* Use Process Table (ISA 3) */
473 #define LPCR_HR ASM_CONST(0x0000000000100000)
475 #define SPRN_LPID 0x13F /* Logical Partition Identifier */
477 #define LPID_RSVD_POWER7 0x3ff /* Reserved LPID for partn switching */
478 #define LPID_RSVD 0xfff /* Reserved LPID for partn switching */
479 #define SPRN_HMER 0x150 /* Hypervisor maintenance exception reg */
481 #define SPRN_HMEER 0x151 /* Hyp maintenance exception enable reg */
482 #define SPRN_PCR 0x152 /* Processor compatibility register */
483 #define PCR_VEC_DIS (__MASK(63-0)) /* Vec. disable (bit NA since POWER8) */
493 #define PCR_ARCH_300 0x10 /* Architecture 3.00 */
494 #define PCR_ARCH_207 0x8 /* Architecture 2.07 */
495 #define PCR_ARCH_206 0x4 /* Architecture 2.06 */
496 #define PCR_ARCH_205 0x2 /* Architecture 2.05 */
499 #define SPRN_HEIR 0x153 /* Hypervisor Emulated Instruction Register */
500 #define SPRN_TLBINDEXR 0x154 /* P7 TLB control register */
501 #define SPRN_TLBVPNR 0x155 /* P7 TLB control register */
502 #define SPRN_TLBRPNR 0x156 /* P7 TLB control register */
503 #define SPRN_TLBLPIDR 0x157 /* P7 TLB control register */
504 #define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */
505 #define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */
506 #define SPRN_DBAT1L 0x21B /* Data BAT 1 Lower Register */
507 #define SPRN_DBAT1U 0x21A /* Data BAT 1 Upper Register */
508 #define SPRN_DBAT2L 0x21D /* Data BAT 2 Lower Register */
509 #define SPRN_DBAT2U 0x21C /* Data BAT 2 Upper Register */
510 #define SPRN_DBAT3L 0x21F /* Data BAT 3 Lower Register */
511 #define SPRN_DBAT3U 0x21E /* Data BAT 3 Upper Register */
512 #define SPRN_DBAT4L 0x239 /* Data BAT 4 Lower Register */
513 #define SPRN_DBAT4U 0x238 /* Data BAT 4 Upper Register */
514 #define SPRN_DBAT5L 0x23B /* Data BAT 5 Lower Register */
515 #define SPRN_DBAT5U 0x23A /* Data BAT 5 Upper Register */
516 #define SPRN_DBAT6L 0x23D /* Data BAT 6 Lower Register */
517 #define SPRN_DBAT6U 0x23C /* Data BAT 6 Upper Register */
518 #define SPRN_DBAT7L 0x23F /* Data BAT 7 Lower Register */
519 #define SPRN_DBAT7U 0x23E /* Data BAT 7 Upper Register */
520 #define SPRN_PPR 0x380 /* SMT Thread status Register */
521 #define SPRN_TSCR 0x399 /* Thread Switch Control Register */
523 #define SPRN_DEC 0x016 /* Decrement Register */
524 #define SPRN_PIT 0x3DB /* Programmable Interval Timer (40x/BOOKE) */
526 #define SPRN_DER 0x095 /* Debug Enable Register */
527 #define DER_RSTE 0x40000000 /* Reset Interrupt */
528 #define DER_CHSTPE 0x20000000 /* Check Stop */
529 #define DER_MCIE 0x10000000 /* Machine Check Interrupt */
530 #define DER_EXTIE 0x02000000 /* External Interrupt */
531 #define DER_ALIE 0x01000000 /* Alignment Interrupt */
532 #define DER_PRIE 0x00800000 /* Program Interrupt */
533 #define DER_FPUVIE 0x00400000 /* FP Unavailable Interrupt */
534 #define DER_DECIE 0x00200000 /* Decrementer Interrupt */
535 #define DER_SYSIE 0x00040000 /* System Call Interrupt */
536 #define DER_TRE 0x00020000 /* Trace Interrupt */
537 #define DER_SEIE 0x00004000 /* FP SW Emulation Interrupt */
538 #define DER_ITLBMSE 0x00002000 /* Imp. Spec. Instruction TLB Miss */
539 #define DER_ITLBERE 0x00001000 /* Imp. Spec. Instruction TLB Error */
540 #define DER_DTLBMSE 0x00000800 /* Imp. Spec. Data TLB Miss */
541 #define DER_DTLBERE 0x00000400 /* Imp. Spec. Data TLB Error */
542 #define DER_LBRKE 0x00000008 /* Load/Store Breakpoint Interrupt */
543 #define DER_IBRKE 0x00000004 /* Instruction Breakpoint Interrupt */
544 #define DER_EBRKE 0x00000002 /* External Breakpoint Interrupt */
545 #define DER_DPIE 0x00000001 /* Dev. Port Nonmaskable Request */
546 #define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */
547 #define SPRN_DHDES 0x0B1 /* Directed Hyp. Doorbell Exc. State */
548 #define SPRN_DPDES 0x0B0 /* Directed Priv. Doorbell Exc. State */
549 #define SPRN_EAR 0x11A /* External Address Register */
550 #define SPRN_HASH1 0x3D2 /* Primary Hash Address Register */
551 #define SPRN_HASH2 0x3D3 /* Secondary Hash Address Register */
552 #define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */
589 #define HID0_NOPTI (1<<0) /* No-op dcbt and dcbst instr. */
600 #define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */
604 #define HID1_PC0 (1<<16) /* 7450 PLL_CFG[0] */
612 #define SPRN_HID2 0x3F8 /* Hardware Implementation Register 2 */
613 #define SPRN_HID2_GEKKO 0x398 /* Gekko HID2 Register */
614 #define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */
615 #define SPRN_IABR2 0x3FA /* 83xx */
616 #define SPRN_IBCR 0x135 /* 83xx Insn Breakpoint Control Reg */
617 #define SPRN_IAMR 0x03D /* Instr. Authority Mask Reg */
618 #define SPRN_HID4 0x3F4 /* 970 HID4 */
619 #define HID4_LPES0 (1ul << (63-0)) /* LPAR env. sel. bit 0 */
623 #define HID4_RMOR (0xFFFFul << HID4_RMOR_SH)
626 #define HID4_LPID1_SH 0 /* partition ID top 2 bits */
627 #define SPRN_HID4_GEKKO 0x3F3 /* Gekko HID4 */
628 #define SPRN_HID5 0x3F6 /* 970 HID5 */
629 #define SPRN_HID6 0x3F9 /* BE HID 6 */
630 #define HID6_LB (0x0F<<12) /* Concurrent Large Page Modes */
632 #define SPRN_TSC_CELL 0x399 /* Thread switch control on Cell */
633 #define TSC_CELL_DEC_ENABLE_0 0x400000 /* Decrementer Interrupt */
634 #define TSC_CELL_DEC_ENABLE_1 0x200000 /* Decrementer Interrupt */
635 #define TSC_CELL_EE_ENABLE 0x100000 /* External Interrupt */
636 #define TSC_CELL_EE_BOOST 0x080000 /* External Interrupt Boost */
637 #define SPRN_TSC 0x3FD /* Thread switch control on others */
638 #define SPRN_TST 0x3FC /* Thread switch timeout on others */
640 #define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */
641 #define SPRN_IAC2 0x3F5 /* Instruction Address Compare 2 */
643 #define SPRN_IBAT0L 0x211 /* Instruction BAT 0 Lower Register */
644 #define SPRN_IBAT0U 0x210 /* Instruction BAT 0 Upper Register */
645 #define SPRN_IBAT1L 0x213 /* Instruction BAT 1 Lower Register */
646 #define SPRN_IBAT1U 0x212 /* Instruction BAT 1 Upper Register */
647 #define SPRN_IBAT2L 0x215 /* Instruction BAT 2 Lower Register */
648 #define SPRN_IBAT2U 0x214 /* Instruction BAT 2 Upper Register */
649 #define SPRN_IBAT3L 0x217 /* Instruction BAT 3 Lower Register */
650 #define SPRN_IBAT3U 0x216 /* Instruction BAT 3 Upper Register */
651 #define SPRN_IBAT4L 0x231 /* Instruction BAT 4 Lower Register */
652 #define SPRN_IBAT4U 0x230 /* Instruction BAT 4 Upper Register */
653 #define SPRN_IBAT5L 0x233 /* Instruction BAT 5 Lower Register */
654 #define SPRN_IBAT5U 0x232 /* Instruction BAT 5 Upper Register */
655 #define SPRN_IBAT6L 0x235 /* Instruction BAT 6 Lower Register */
656 #define SPRN_IBAT6U 0x234 /* Instruction BAT 6 Upper Register */
657 #define SPRN_IBAT7L 0x237 /* Instruction BAT 7 Lower Register */
658 #define SPRN_IBAT7U 0x236 /* Instruction BAT 7 Upper Register */
659 #define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */
660 #define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */
662 #define SPRN_ICTRL 0x3F3 /* 1011 7450 icache and interrupt ctrl */
664 #define ICTRL_EICE 0x08000000 /* enable icache parity errs */
665 #define ICTRL_EDC 0x04000000 /* enable dcache parity errs */
666 #define ICTRL_EICP 0x00000100 /* enable icache par. check */
667 #define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */
668 #define SPRN_IMMR 0x27E /* Internal Memory Map Register */
669 #define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Register */
670 #define SPRN_L2CR2 0x3f8
671 #define L2CR_L2E 0x80000000 /* L2 enable */
672 #define L2CR_L2PE 0x40000000 /* L2 parity enable */
673 #define L2CR_L2SIZ_MASK 0x30000000 /* L2 size mask */
674 #define L2CR_L2SIZ_256KB 0x10000000 /* L2 size 256KB */
675 #define L2CR_L2SIZ_512KB 0x20000000 /* L2 size 512KB */
676 #define L2CR_L2SIZ_1MB 0x30000000 /* L2 size 1MB */
677 #define L2CR_L2CLK_MASK 0x0e000000 /* L2 clock mask */
678 #define L2CR_L2CLK_DISABLED 0x00000000 /* L2 clock disabled */
679 #define L2CR_L2CLK_DIV1 0x02000000 /* L2 clock / 1 */
680 #define L2CR_L2CLK_DIV1_5 0x04000000 /* L2 clock / 1.5 */
681 #define L2CR_L2CLK_DIV2 0x08000000 /* L2 clock / 2 */
682 #define L2CR_L2CLK_DIV2_5 0x0a000000 /* L2 clock / 2.5 */
683 #define L2CR_L2CLK_DIV3 0x0c000000 /* L2 clock / 3 */
684 #define L2CR_L2RAM_MASK 0x01800000 /* L2 RAM type mask */
685 #define L2CR_L2RAM_FLOW 0x00000000 /* L2 RAM flow through */
686 #define L2CR_L2RAM_PIPE 0x01000000 /* L2 RAM pipelined */
687 #define L2CR_L2RAM_PIPE_LW 0x01800000 /* L2 RAM pipelined latewr */
688 #define L2CR_L2DO 0x00400000 /* L2 data only */
689 #define L2CR_L2I 0x00200000 /* L2 global invalidate */
690 #define L2CR_L2CTL 0x00100000 /* L2 RAM control */
691 #define L2CR_L2WT 0x00080000 /* L2 write-through */
692 #define L2CR_L2TS 0x00040000 /* L2 test support */
693 #define L2CR_L2OH_MASK 0x00030000 /* L2 output hold mask */
694 #define L2CR_L2OH_0_5 0x00000000 /* L2 output hold 0.5 ns */
695 #define L2CR_L2OH_1_0 0x00010000 /* L2 output hold 1.0 ns */
696 #define L2CR_L2SL 0x00008000 /* L2 DLL slow */
697 #define L2CR_L2DF 0x00004000 /* L2 differential clock */
698 #define L2CR_L2BYP 0x00002000 /* L2 DLL bypass */
699 #define L2CR_L2IP 0x00000001 /* L2 GI in progress */
700 #define L2CR_L2IO_745x 0x00100000 /* L2 instr. only (745x) */
701 #define L2CR_L2DO_745x 0x00010000 /* L2 data only (745x) */
702 #define L2CR_L2REP_745x 0x00001000 /* L2 repl. algorithm (745x) */
703 #define L2CR_L2HWF_745x 0x00000800 /* L2 hardware flush (745x) */
704 #define SPRN_L3CR 0x3FA /* Level 3 Cache Control Register */
705 #define L3CR_L3E 0x80000000 /* L3 enable */
706 #define L3CR_L3PE 0x40000000 /* L3 data parity enable */
707 #define L3CR_L3APE 0x20000000 /* L3 addr parity enable */
708 #define L3CR_L3SIZ 0x10000000 /* L3 size */
709 #define L3CR_L3CLKEN 0x08000000 /* L3 clock enable */
710 #define L3CR_L3RES 0x04000000 /* L3 special reserved bit */
711 #define L3CR_L3CLKDIV 0x03800000 /* L3 clock divisor */
712 #define L3CR_L3IO 0x00400000 /* L3 instruction only */
713 #define L3CR_L3SPO 0x00040000 /* L3 sample point override */
714 #define L3CR_L3CKSP 0x00030000 /* L3 clock sample point */
715 #define L3CR_L3PSP 0x0000e000 /* L3 P-clock sample point */
716 #define L3CR_L3REP 0x00001000 /* L3 replacement algorithm */
717 #define L3CR_L3HWF 0x00000800 /* L3 hardware flush */
718 #define L3CR_L3I 0x00000400 /* L3 global invalidate */
719 #define L3CR_L3RT 0x00000300 /* L3 SRAM type */
720 #define L3CR_L3NIRCA 0x00000080 /* L3 non-integer ratio clock adj. */
721 #define L3CR_L3DO 0x00000040 /* L3 data only mode */
722 #define L3CR_PMEN 0x00000004 /* L3 private memory enable */
723 #define L3CR_PMSIZ 0x00000001 /* L3 private memory size */
725 #define SPRN_MSSCR0 0x3f6 /* Memory Subsystem Control Register 0 */
726 #define SPRN_MSSSR0 0x3f7 /* Memory Subsystem Status Register 1 */
727 #define SPRN_LDSTCR 0x3f8 /* Load/Store control register */
728 #define SPRN_LDSTDB 0x3f4 /* */
729 #define SPRN_LR 0x008 /* Link Register */
731 #define SPRN_PIR 0x3FF /* Processor Identification Register */
733 #define SPRN_TIR 0x1BE /* Thread Identification Register */
734 #define SPRN_PTCR 0x1D0 /* Partition table control Register */
735 #define SPRN_PSPB 0x09F /* Problem State Priority Boost reg */
736 #define SPRN_PTEHI 0x3D5 /* 981 7450 PTE HI word (S/W TLB load) */
737 #define SPRN_PTELO 0x3D6 /* 982 7450 PTE LO word (S/W TLB load) */
738 #define SPRN_PURR 0x135 /* Processor Utilization of Resources Reg */
739 #define SPRN_PVR 0x11F /* Processor Version Register */
740 #define SPRN_RPA 0x3D6 /* Required Physical Address Register */
741 #define SPRN_SDA 0x3BF /* Sampled Data Address Register */
742 #define SPRN_SDR1 0x019 /* MMU Hash Base Register */
743 #define SPRN_ASR 0x118 /* Address Space Register */
744 #define SPRN_SIA 0x3BB /* Sampled Instruction Address Register */
745 #define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */
746 #define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */
747 #define SPRN_SPRG2 0x112 /* Special Purpose Register General 2 */
748 #define SPRN_SPRG3 0x113 /* Special Purpose Register General 3 */
749 #define SPRN_USPRG3 0x103 /* SPRG3 userspace read */
750 #define SPRN_SPRG4 0x114 /* Special Purpose Register General 4 */
751 #define SPRN_USPRG4 0x104 /* SPRG4 userspace read */
752 #define SPRN_SPRG5 0x115 /* Special Purpose Register General 5 */
753 #define SPRN_USPRG5 0x105 /* SPRG5 userspace read */
754 #define SPRN_SPRG6 0x116 /* Special Purpose Register General 6 */
755 #define SPRN_USPRG6 0x106 /* SPRG6 userspace read */
756 #define SPRN_SPRG7 0x117 /* Special Purpose Register General 7 */
757 #define SPRN_USPRG7 0x107 /* SPRG7 userspace read */
758 #define SPRN_SRR0 0x01A /* Save/Restore Register 0 */
759 #define SPRN_SRR1 0x01B /* Save/Restore Register 1 */
769 #define SRR1_MSR_BITS (~0x783f0000UL)
772 #define SRR1_ISI_NOPT 0x40000000 /* ISI: Not found in hash */
773 #define SRR1_ISI_N_G_OR_CIP 0x10000000 /* ISI: Access is no-exec or G or CI for a prefixed instru…
774 #define SRR1_ISI_PROT 0x08000000 /* ISI: Other protection fault */
775 #define SRR1_WAKEMASK 0x00380000 /* reason for wakeup */
776 #define SRR1_WAKEMASK_P8 0x003c0000 /* reason for wakeup on POWER8 and 9 */
777 #define SRR1_WAKEMCE_RESVD 0x003c0000 /* Unused/reserved value used by MCE wakeup to indicate cau…
778 #define SRR1_WAKESYSERR 0x00300000 /* System error */
779 #define SRR1_WAKEEE 0x00200000 /* External interrupt */
780 #define SRR1_WAKEHVI 0x00240000 /* Hypervisor Virtualization Interrupt (P9) */
781 #define SRR1_WAKEMT 0x00280000 /* mtctrl */
782 #define SRR1_WAKEHMI 0x00280000 /* Hypervisor maintenance */
783 #define SRR1_WAKEDEC 0x00180000 /* Decrementer interrupt */
784 #define SRR1_WAKEDBELL 0x00140000 /* Privileged doorbell on P8 */
785 #define SRR1_WAKETHERM 0x00100000 /* Thermal management interrupt */
786 #define SRR1_WAKERESET 0x00100000 /* System reset */
787 #define SRR1_WAKEHDBELL 0x000c0000 /* Hypervisor doorbell on P8 */
788 #define SRR1_WAKESTATE 0x00030000 /* Powersave exit mask [46:47] */
789 #define SRR1_WS_HVLOSS 0x00030000 /* HV resources not maintained */
790 #define SRR1_WS_GPRLOSS 0x00020000 /* GPRs not maintained */
791 #define SRR1_WS_NOLOSS 0x00010000 /* All resources maintained */
792 #define SRR1_PROGTM 0x00200000 /* TM Bad Thing */
793 #define SRR1_PROGFPE 0x00100000 /* Floating Point Enabled */
794 #define SRR1_PROGILL 0x00080000 /* Illegal instruction */
795 #define SRR1_PROGPRIV 0x00040000 /* Privileged instruction */
796 #define SRR1_PROGTRAP 0x00020000 /* Trap */
797 #define SRR1_PROGADDR 0x00010000 /* SRR0 contains subsequent addr */
799 #define SRR1_MCE_MCP 0x00080000 /* Machine check signal caused interrupt */
800 #define SRR1_BOUNDARY 0x10000000 /* Prefixed instruction crosses 64-byte boundary */
801 #define SRR1_PREFIXED 0x20000000 /* Exception caused by prefixed instruction */
803 #define SPRN_HSRR0 0x13A /* Save/Restore Register 0 */
804 #define SPRN_HSRR1 0x13B /* Save/Restore Register 1 */
805 #define HSRR1_DENORM 0x00100000 /* Denorm exception */
806 #define HSRR1_HISI_WRITE 0x00010000 /* HISI bcs couldn't update mem */
808 #define SPRN_TBCTL 0x35f /* PA6T Timebase control register */
809 #define TBCTL_FREEZE 0x0000000000000000ull /* Freeze all tbs */
810 #define TBCTL_RESTART 0x0000000100000000ull /* Restart all tbs */
811 #define TBCTL_UPDATE_UPPER 0x0000000200000000ull /* Set upper 32 bits */
812 #define TBCTL_UPDATE_LOWER 0x0000000300000000ull /* Set lower 32 bits */
815 #define SPRN_SVR 0x11E /* System Version Register */
817 #define SPRN_THRM1 0x3FC /* Thermal Management Register 1 */
821 #define THRM1_THRES(x) ((x&0x7f)<<23)
822 #define THRM3_SITV(x) ((x & 0x1fff) << 1)
825 #define THRM1_V (1<<0)
826 #define SPRN_THRM2 0x3FD /* Thermal Management Register 2 */
827 #define SPRN_THRM3 0x3FE /* Thermal Management Register 3 */
828 #define THRM3_E (1<<0)
829 #define SPRN_TLBMISS 0x3D4 /* 980 7450 TLB Miss Register */
830 #define SPRN_UMMCR0 0x3A8 /* User Monitor Mode Control Register 0 */
831 #define SPRN_UMMCR1 0x3AC /* User Monitor Mode Control Register 0 */
832 #define SPRN_UPMC1 0x3A9 /* User Performance Counter Register 1 */
833 #define SPRN_UPMC2 0x3AA /* User Performance Counter Register 2 */
834 #define SPRN_UPMC3 0x3AD /* User Performance Counter Register 3 */
835 #define SPRN_UPMC4 0x3AE /* User Performance Counter Register 4 */
836 #define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register */
837 #define SPRN_VRSAVE 0x100 /* Vector Register Save Register */
838 #define SPRN_XER 0x001 /* Fixed Point Exception Register */
840 #define SPRN_MMCR0_GEKKO 0x3B8 /* Gekko Monitor Mode Control Register 0 */
841 #define SPRN_MMCR1_GEKKO 0x3BC /* Gekko Monitor Mode Control Register 1 */
842 #define SPRN_PMC1_GEKKO 0x3B9 /* Gekko Performance Monitor Control 1 */
843 #define SPRN_PMC2_GEKKO 0x3BA /* Gekko Performance Monitor Control 2 */
844 #define SPRN_PMC3_GEKKO 0x3BD /* Gekko Performance Monitor Control 3 */
845 #define SPRN_PMC4_GEKKO 0x3BE /* Gekko Performance Monitor Control 4 */
846 #define SPRN_WPAR_GEKKO 0x399 /* Gekko Write Pipe Address Register */
848 #define SPRN_SCOMC 0x114 /* SCOM Access Control */
849 #define SPRN_SCOMD 0x115 /* SCOM Access DATA */
854 #define MMCR0_FC 0x80000000UL /* freeze counters */
855 #define MMCR0_FCS 0x40000000UL /* freeze in supervisor state */
857 #define MMCR0_FCP 0x20000000UL /* freeze in problem state */
859 #define MMCR0_FCM1 0x10000000UL /* freeze counters while MSR mark = 1 */
860 #define MMCR0_FCM0 0x08000000UL /* freeze counters while MSR mark = 0 */
861 #define MMCR0_PMXE ASM_CONST(0x04000000) /* perf mon exception enable */
862 #define MMCR0_FCECE ASM_CONST(0x02000000) /* freeze ctrs on enabled cond or event */
863 #define MMCR0_TBEE 0x00400000UL /* time base exception enable */
864 #define MMCR0_BHRBA 0x00200000UL /* BHRB Access allowed in userspace */
865 #define MMCR0_EBE 0x00100000UL /* Event based branch enable */
866 #define MMCR0_PMCC 0x000c0000UL /* PMC control */
867 #define MMCR0_PMCC_U6 0x00080000UL /* PMC1-6 are R/W by user (PR) */
868 #define MMCR0_PMC1CE 0x00008000UL /* PMC1 count enable*/
869 #define MMCR0_PMCjCE ASM_CONST(0x00004000) /* PMCj count enable*/
870 #define MMCR0_TRIGGER 0x00002000UL /* TRIGGER enable */
871 #define MMCR0_PMAO_SYNC ASM_CONST(0x00000800) /* PMU intr is synchronous */
872 #define MMCR0_C56RUN ASM_CONST(0x00000100) /* PMC5/6 count when RUN=0 */
873 /* performance monitor alert has occurred, set to 0 after handling exception */
874 #define MMCR0_PMAO ASM_CONST(0x00000080)
875 #define MMCR0_SHRFC 0x00000040UL /* SHRre freeze conditions between threads */
876 #define MMCR0_FC56 0x00000010UL /* freeze counters 5 and 6 */
877 #define MMCR0_FCTI 0x00000008UL /* freeze counters in tags inactive mode */
878 #define MMCR0_FCTA 0x00000004UL /* freeze counters in tags active mode */
879 #define MMCR0_FCWAIT 0x00000002UL /* freeze counter in WAIT state */
880 #define MMCR0_FCHV 0x00000001UL /* freeze conditions in hypervisor mode */
886 #define SPRN_MMCRA 0x312
887 #define MMCRA_SDSYNC 0x80000000UL /* SDAR synced with SIAR */
888 #define MMCRA_SDAR_DCACHE_MISS 0x40000000UL
889 #define MMCRA_SDAR_ERAT_MISS 0x20000000UL
890 #define MMCRA_SIHV 0x10000000UL /* state of MSR HV when SIAR set */
891 #define MMCRA_SIPR 0x08000000UL /* state of MSR PR when SIAR set */
892 #define MMCRA_SLOT 0x07000000UL /* SLOT bits (37-39) */
894 #define MMCRA_SAMPLE_ENABLE 0x00000001UL /* enable sampling */
895 #define MMCRA_BHRB_DISABLE _UL(0x2000000000) // BHRB disable bit for ISA v3.1
896 #define POWER6_MMCRA_SDSYNC 0x0000080000000000ULL /* SDAR/SIAR synced */
897 #define POWER6_MMCRA_SIHV 0x0000040000000000ULL
898 #define POWER6_MMCRA_SIPR 0x0000020000000000ULL
899 #define POWER6_MMCRA_THRM 0x00000020UL
900 #define POWER6_MMCRA_OTHER 0x0000000EUL
902 #define POWER7P_MMCRA_SIAR_VALID 0x10000000 /* P7+ SIAR contents valid */
903 #define POWER7P_MMCRA_SDAR_VALID 0x08000000 /* P7+ SDAR contents valid */
911 #define BESCR_GE 0x8000000000000000ULL /* Global Enable */
924 #define SIER_SIPR 0x2000000 /* Sampled MSR_PR */
925 #define SIER_SIHV 0x1000000 /* Sampled MSR_HV */
926 #define SIER_SIAR_VALID 0x0400000 /* SIAR contents valid */
927 #define SIER_SDAR_VALID 0x0200000 /* SDAR contents valid */
942 #define MMCR2_USER_MASK 0x4020100804020000UL /* (FC1P|FC2P|FC3P|FC4P|FC5P|FC6P) */
943 #define SIER_USER_MASK 0x7fffffUL
946 #define PA6T_MMCR0_EN0 0x0000000000000001UL
947 #define PA6T_MMCR0_EN1 0x0000000000000002UL
948 #define PA6T_MMCR0_EN2 0x0000000000000004UL
949 #define PA6T_MMCR0_EN3 0x0000000000000008UL
950 #define PA6T_MMCR0_EN4 0x0000000000000010UL
951 #define PA6T_MMCR0_EN5 0x0000000000000020UL
952 #define PA6T_MMCR0_SUPEN 0x0000000000000040UL
953 #define PA6T_MMCR0_PREN 0x0000000000000080UL
954 #define PA6T_MMCR0_HYPEN 0x0000000000000100UL
955 #define PA6T_MMCR0_FCM0 0x0000000000000200UL
956 #define PA6T_MMCR0_FCM1 0x0000000000000400UL
957 #define PA6T_MMCR0_INTGEN 0x0000000000000800UL
958 #define PA6T_MMCR0_INTEN0 0x0000000000001000UL
959 #define PA6T_MMCR0_INTEN1 0x0000000000002000UL
960 #define PA6T_MMCR0_INTEN2 0x0000000000004000UL
961 #define PA6T_MMCR0_INTEN3 0x0000000000008000UL
962 #define PA6T_MMCR0_INTEN4 0x0000000000010000UL
963 #define PA6T_MMCR0_INTEN5 0x0000000000020000UL
964 #define PA6T_MMCR0_DISCNT 0x0000000000040000UL
965 #define PA6T_MMCR0_UOP 0x0000000000080000UL
966 #define PA6T_MMCR0_TRG 0x0000000000100000UL
967 #define PA6T_MMCR0_TRGEN 0x0000000000200000UL
968 #define PA6T_MMCR0_TRGREG 0x0000000001600000UL
969 #define PA6T_MMCR0_SIARLOG 0x0000000002000000UL
970 #define PA6T_MMCR0_SDARLOG 0x0000000004000000UL
971 #define PA6T_MMCR0_PROEN 0x0000000008000000UL
972 #define PA6T_MMCR0_PROLOG 0x0000000010000000UL
973 #define PA6T_MMCR0_DAMEN2 0x0000000020000000UL
974 #define PA6T_MMCR0_DAMEN3 0x0000000040000000UL
975 #define PA6T_MMCR0_DAMEN4 0x0000000080000000UL
976 #define PA6T_MMCR0_DAMEN5 0x0000000100000000UL
977 #define PA6T_MMCR0_DAMSEL2 0x0000000200000000UL
978 #define PA6T_MMCR0_DAMSEL3 0x0000000400000000UL
979 #define PA6T_MMCR0_DAMSEL4 0x0000000800000000UL
980 #define PA6T_MMCR0_DAMSEL5 0x0000001000000000UL
981 #define PA6T_MMCR0_HANDDIS 0x0000002000000000UL
982 #define PA6T_MMCR0_PCTEN 0x0000004000000000UL
983 #define PA6T_MMCR0_SOCEN 0x0000008000000000UL
984 #define PA6T_MMCR0_SOCMOD 0x0000010000000000UL
987 #define PA6T_MMCR1_ES2 0x00000000000000ffUL
988 #define PA6T_MMCR1_ES3 0x000000000000ff00UL
989 #define PA6T_MMCR1_ES4 0x0000000000ff0000UL
990 #define PA6T_MMCR1_ES5 0x00000000ff000000UL
992 #define SPRN_PA6T_UPMC0 771 /* User PerfMon Counter 0 */
998 #define SPRN_PA6T_UMMCR0 779 /* User Monitor Mode Control Register 0 */
1008 #define SPRN_PA6T_TSR0 793 /* Timestamp Register 0 */
1018 #define SPRN_PA6T_IMA0 880 /* Instruction Match Array 0 */
1036 #define SPRN_MMCR0 952 /* Monitor Mode Control Register 0 */
1037 #define MMCR0_FC 0x80000000UL /* freeze counters */
1038 #define MMCR0_FCS 0x40000000UL /* freeze in supervisor state */
1039 #define MMCR0_FCP 0x20000000UL /* freeze in problem state */
1040 #define MMCR0_FCM1 0x10000000UL /* freeze counters while MSR mark = 1 */
1041 #define MMCR0_FCM0 0x08000000UL /* freeze counters while MSR mark = 0 */
1042 #define MMCR0_PMXE 0x04000000UL /* performance monitor exception enable */
1043 #define MMCR0_FCECE 0x02000000UL /* freeze ctrs on enabled cond or event */
1044 #define MMCR0_TBEE 0x00400000UL /* time base exception enable */
1045 #define MMCR0_PMC1CE 0x00008000UL /* PMC1 count enable*/
1046 #define MMCR0_PMCnCE 0x00004000UL /* count enable for all but PMC 1*/
1047 #define MMCR0_TRIGGER 0x00002000UL /* TRIGGER enable */
1048 #define MMCR0_PMC1SEL 0x00001fc0UL /* PMC 1 Event */
1049 #define MMCR0_PMC2SEL 0x0000003fUL /* PMC 2 Event */
1052 #define MMCR1_PMC3SEL 0xf8000000UL /* PMC 3 Event */
1053 #define MMCR1_PMC4SEL 0x07c00000UL /* PMC 4 Event */
1054 #define MMCR1_PMC5SEL 0x003e0000UL /* PMC 5 Event */
1055 #define MMCR1_PMC6SEL 0x0001f800UL /* PMC 6 Event */
1070 #define MMCR0_PMC2_DCACHEMISS 0x6
1071 #define MMCR0_PMC2_CYCLES 0x1
1072 #define MMCR0_PMC2_ITLB 0x7
1073 #define MMCR0_PMC2_LOADMISSTIME 0x5
1260 .long (0xfc00058e | ((0xff) << 17) | ((REG) << 11) | (1 << 25))
1262 #define MTFSF_L(REG) mtfsf 0xff, (REG)
1267 #define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */
1268 #define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */
1277 #define PVR_FAM(pvr) (((pvr) >> 20) & 0xFFF) /* Family field */
1278 #define PVR_MEM(pvr) (((pvr) >> 16) & 0xF) /* Member field */
1279 #define PVR_CORE(pvr) (((pvr) >> 12) & 0xF) /* Core field */
1280 #define PVR_CFG(pvr) (((pvr) >> 8) & 0xF) /* Configuration field */
1281 #define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */
1282 #define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */
1286 #define PVR_403GA 0x00200000
1287 #define PVR_403GB 0x00200100
1288 #define PVR_403GC 0x00200200
1289 #define PVR_403GCX 0x00201400
1290 #define PVR_405GP 0x40110000
1291 #define PVR_476 0x11a52000
1292 #define PVR_476FPE 0x7ff50000
1293 #define PVR_STB03XXX 0x40310000
1294 #define PVR_NP405H 0x41410000
1295 #define PVR_NP405L 0x41610000
1296 #define PVR_601 0x00010000
1297 #define PVR_602 0x00050000
1298 #define PVR_603 0x00030000
1299 #define PVR_603e 0x00060000
1300 #define PVR_603ev 0x00070000
1301 #define PVR_603r 0x00071000
1302 #define PVR_604 0x00040000
1303 #define PVR_604e 0x00090000
1304 #define PVR_604r 0x000A0000
1305 #define PVR_620 0x00140000
1306 #define PVR_740 0x00080000
1308 #define PVR_740P 0x10080000
1310 #define PVR_7400 0x000C0000
1311 #define PVR_7410 0x800C0000
1312 #define PVR_7450 0x80000000
1313 #define PVR_8540 0x80200000
1314 #define PVR_8560 0x80200000
1315 #define PVR_VER_E500V1 0x8020
1316 #define PVR_VER_E500V2 0x8021
1317 #define PVR_VER_E500MC 0x8023
1318 #define PVR_VER_E5500 0x8024
1319 #define PVR_VER_E6500 0x8040
1327 #define PVR_8xx 0x00500000
1329 #define PVR_8240 0x00810100
1330 #define PVR_8245 0x80811014
1334 #define PVR_476_ISS 0x00052000
1337 #define PVR_NORTHSTAR 0x0033
1338 #define PVR_PULSAR 0x0034
1339 #define PVR_POWER4 0x0035
1340 #define PVR_ICESTAR 0x0036
1341 #define PVR_SSTAR 0x0037
1342 #define PVR_POWER4p 0x0038
1343 #define PVR_970 0x0039
1344 #define PVR_POWER5 0x003A
1345 #define PVR_POWER5p 0x003B
1346 #define PVR_970FX 0x003C
1347 #define PVR_POWER6 0x003E
1348 #define PVR_POWER7 0x003F
1349 #define PVR_630 0x0040
1350 #define PVR_630p 0x0041
1351 #define PVR_970MP 0x0044
1352 #define PVR_970GX 0x0045
1353 #define PVR_POWER7p 0x004A
1354 #define PVR_POWER8E 0x004B
1355 #define PVR_POWER8NVL 0x004C
1356 #define PVR_POWER8 0x004D
1357 #define PVR_POWER9 0x004E
1358 #define PVR_POWER10 0x0080
1359 #define PVR_BE 0x0070
1360 #define PVR_PA6T 0x0090
1363 #define PVR_ARCH_204 0x0f000001
1364 #define PVR_ARCH_205 0x0f000002
1365 #define PVR_ARCH_206 0x0f000003
1366 #define PVR_ARCH_206p 0x0f100003
1367 #define PVR_ARCH_207 0x0f000004
1368 #define PVR_ARCH_300 0x0f000005
1369 #define PVR_ARCH_31 0x0f000006
1374 asm volatile("mfmsr %0" : "=r" (rval) : \
1377 #define __mtmsrd(v, l) asm volatile("mtmsrd %0," __stringify(l) \
1379 #define mtmsr(v) __mtmsrd((v), 0)
1382 #define mtmsr(v) asm volatile("mtmsr %0" : \
1390 asm volatile(__MTMSR " %0; " ASM_FTR_IFCLR("isync", "nop", %1) : : in mtmsr_isync()
1395 asm volatile("mfspr %0," __stringify(rn) \
1398 #define mtspr(rn, v) asm volatile("mtspr " __stringify(rn) ",%0" : \
1402 #define wrtspr(rn) asm volatile("mtspr " __stringify(rn) ",0" : \
1408 asm volatile("wrteei %0" : : "i" ((val & MSR_EE) ? 1 : 0) : "memory"); in wrtee()
1410 asm volatile("wrtee %0" : : "r" (val) : "memory"); in wrtee()
1425 "90: mfspr %0, %2;\n" \
1427 "97: cmpwi %0,0;\n" \
1434 asm volatile("mftbl %0" : "=r" (rval)); rval;})
1437 asm volatile("mfspr %0, %1" : \
1443 asm volatile("mftbu %0" : "=r" (rval)); rval;})
1446 asm volatile("mfspr %0, %1" : "=r" (rval) : \
1450 #define mttbl(v) asm volatile("mttbl %0":: "r"(v))
1451 #define mttbu(v) asm volatile("mttbu %0":: "r"(v))
1455 asm volatile("mfsrin %0,%1" : "=r" (rval) : "r" (v)); \
1460 asm volatile("mtsrin %0, %1" : : "r" (val), "r" (idx)); in mtsrin()
1484 asm volatile("sync; mtspr %0,%1; isync":: "i"(SPRN_HID0), "r"(hid0)); in update_power8_hid0()