boot/dts/tqm8555.dts

1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /dts-v1/;
13 	#address-cells = <1>;
14 	#size-cells = <1>;
25 		#address-cells = <1>;
26 		#size-cells = <0>;
31 			d-cache-line-size = <32>;
32 			i-cache-line-size = <32>;
33 			d-cache-size = <32768>;
34 			i-cache-size = <32768>;
35 			timebase-frequency = <0>;
36 			bus-frequency = <0>;
37 			clock-frequency = <0>;
38 			next-level-cache = <&L2>;
48 		#address-cells = <1>;
49 		#size-cells = <1>;
51 		ranges = <0x0 0xe0000000 0x100000>;
52 		bus-frequency = <0>;
53 		compatible = "fsl,mpc8555-immr", "simple-bus";
55 		ecm-law@0 {
56 			compatible = "fsl,ecm-law";
58 			fsl,num-laws = <8>;
62 			compatible = "fsl,mpc8555-ecm", "fsl,ecm";
65 			interrupt-parent = <&mpic>;
68 		memory-controller@2000 {
69 			compatible = "fsl,mpc8540-memory-controller";
71 			interrupt-parent = <&mpic>;
75 		L2: l2-cache-controller@20000 {
76 			compatible = "fsl,mpc8540-l2-cache-controller";
78 			cache-line-size = <32>;
79 			cache-size = <0x40000>;	// L2, 256K
80 			interrupt-parent = <&mpic>;
85 			#address-cells = <1>;
86 			#size-cells = <0>;
87 			cell-index = <0>;
88 			compatible = "fsl-i2c";
91 			interrupt-parent = <&mpic>;
105 		dma@21300 {
106 			#address-cells = <1>;
107 			#size-cells = <1>;
108 			compatible = "fsl,mpc8555-dma", "fsl,eloplus-dma";
110 			ranges = <0x0 0x21100 0x200>;
111 			cell-index = <0>;
112 			dma-channel@0 {
113 				compatible = "fsl,mpc8555-dma-channel",
114 						"fsl,eloplus-dma-channel";
116 				cell-index = <0>;
117 				interrupt-parent = <&mpic>;
120 			dma-channel@80 {
121 				compatible = "fsl,mpc8555-dma-channel",
122 						"fsl,eloplus-dma-channel";
124 				cell-index = <1>;
125 				interrupt-parent = <&mpic>;
128 			dma-channel@100 {
129 				compatible = "fsl,mpc8555-dma-channel",
130 						"fsl,eloplus-dma-channel";
132 				cell-index = <2>;
133 				interrupt-parent = <&mpic>;
136 			dma-channel@180 {
137 				compatible = "fsl,mpc8555-dma-channel",
138 						"fsl,eloplus-dma-channel";
140 				cell-index = <3>;
141 				interrupt-parent = <&mpic>;
147 			#address-cells = <1>;
148 			#size-cells = <1>;
149 			cell-index = <0>;
154 			ranges = <0x0 0x24000 0x1000>;
155 			local-mac-address = [ 00 00 00 00 00 00 ];
157 			interrupt-parent = <&mpic>;
158 			tbi-handle = <&tbi0>;
159 			phy-handle = <&phy2>;
162 				#address-cells = <1>;
163 				#size-cells = <0>;
164 				compatible = "fsl,gianfar-mdio";
167 				phy1: ethernet-phy@1 {
168 					interrupt-parent = <&mpic>;
172 				phy2: ethernet-phy@2 {
173 					interrupt-parent = <&mpic>;
177 				phy3: ethernet-phy@3 {
178 					interrupt-parent = <&mpic>;
182 				tbi0: tbi-phy@11 {
184 					device_type = "tbi-phy";
190 			#address-cells = <1>;
191 			#size-cells = <1>;
192 			cell-index = <1>;
197 			ranges = <0x0 0x25000 0x1000>;
198 			local-mac-address = [ 00 00 00 00 00 00 ];
200 			interrupt-parent = <&mpic>;
201 			tbi-handle = <&tbi1>;
202 			phy-handle = <&phy1>;
205 				#address-cells = <1>;
206 				#size-cells = <0>;
207 				compatible = "fsl,gianfar-tbi";
210 				tbi1: tbi-phy@11 {
212 					device_type = "tbi-phy";
218 			cell-index = <0>;
222 			clock-frequency = <0>; 	// should we fill in in uboot?
224 			interrupt-parent = <&mpic>;
228 			cell-index = <1>;
232 			clock-frequency = <0>; 	// should we fill in in uboot?
234 			interrupt-parent = <&mpic>;
241 			interrupt-parent = <&mpic>;
242 			fsl,num-channels = <4>;
243 			fsl,channel-fifo-len = <24>;
244 			fsl,exec-units-mask = <0x7e>;
245 			fsl,descriptor-types-mask = <0x01010ebf>;
249 			interrupt-controller;
250 			#address-cells = <0>;
251 			#interrupt-cells = <2>;
253 			device_type = "open-pic";
254 			compatible = "chrp,open-pic";
258 			#address-cells = <1>;
259 			#size-cells = <1>;
260 			compatible = "fsl,mpc8555-cpm", "fsl,cpm2", "simple-bus";
262 			ranges;
265 				#address-cells = <1>;
266 				#size-cells = <1>;
267 				ranges = <0 0x80000 0x10000>;
270 					compatible = "fsl,cpm-muram-data";
276 				compatible = "fsl,mpc8555-brg",
277 				             "fsl,cpm2-brg",
278 				             "fsl,cpm-brg";
280 				clock-frequency = <0>;
284 				interrupt-controller;
285 				#address-cells = <0>;
286 				#interrupt-cells = <2>;
288 				interrupt-parent = <&mpic>;
290 				compatible = "fsl,mpc8555-cpm-pic", "fsl,cpm2-pic";
296 		#interrupt-cells = <1>;
297 		#size-cells = <2>;
298 		#address-cells = <3>;
299 		compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
302 		clock-frequency = <66666666>;
303 		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
304 		interrupt-map = <
316 		interrupt-parent = <&mpic>;
318 		bus-range = <0 0>;
319 		ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000