Lines Matching +full:cell +full:- +full:index

1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /dts-v1/;
13 #address-cells = <1>;
14 #size-cells = <1>;
26 #address-cells = <1>;
27 #size-cells = <0>;
32 d-cache-line-size = <32>;
33 i-cache-line-size = <32>;
34 d-cache-size = <32768>;
35 i-cache-size = <32768>;
36 timebase-frequency = <0>;
37 bus-frequency = <0>;
38 clock-frequency = <0>;
39 next-level-cache = <&L2>;
49 #address-cells = <1>;
50 #size-cells = <1>;
53 bus-frequency = <0>;
54 compatible = "fsl,mpc8540-immr", "simple-bus";
56 ecm-law@0 {
57 compatible = "fsl,ecm-law";
59 fsl,num-laws = <8>;
63 compatible = "fsl,mpc8540-ecm", "fsl,ecm";
66 interrupt-parent = <&mpic>;
69 memory-controller@2000 {
70 compatible = "fsl,mpc8540-memory-controller";
72 interrupt-parent = <&mpic>;
76 L2: l2-cache-controller@20000 {
77 compatible = "fsl,mpc8540-l2-cache-controller";
79 cache-line-size = <32>;
80 cache-size = <0x40000>; // L2, 256K
81 interrupt-parent = <&mpic>;
86 #address-cells = <1>;
87 #size-cells = <0>;
88 cell-index = <0>;
89 compatible = "fsl-i2c";
92 interrupt-parent = <&mpic>;
107 #address-cells = <1>;
108 #size-cells = <1>;
109 compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma";
112 cell-index = <0>;
113 dma-channel@0 {
114 compatible = "fsl,mpc8540-dma-channel",
115 "fsl,eloplus-dma-channel";
117 cell-index = <0>;
118 interrupt-parent = <&mpic>;
121 dma-channel@80 {
122 compatible = "fsl,mpc8540-dma-channel",
123 "fsl,eloplus-dma-channel";
125 cell-index = <1>;
126 interrupt-parent = <&mpic>;
129 dma-channel@100 {
130 compatible = "fsl,mpc8540-dma-channel",
131 "fsl,eloplus-dma-channel";
133 cell-index = <2>;
134 interrupt-parent = <&mpic>;
137 dma-channel@180 {
138 compatible = "fsl,mpc8540-dma-channel",
139 "fsl,eloplus-dma-channel";
141 cell-index = <3>;
142 interrupt-parent = <&mpic>;
148 #address-cells = <1>;
149 #size-cells = <1>;
150 cell-index = <0>;
156 local-mac-address = [ 00 00 00 00 00 00 ];
158 interrupt-parent = <&mpic>;
159 phy-handle = <&phy2>;
162 #address-cells = <1>;
163 #size-cells = <0>;
164 compatible = "fsl,gianfar-mdio";
167 phy1: ethernet-phy@1 {
168 interrupt-parent = <&mpic>;
172 phy2: ethernet-phy@2 {
173 interrupt-parent = <&mpic>;
177 phy3: ethernet-phy@3 {
178 interrupt-parent = <&mpic>;
182 tbi0: tbi-phy@11 {
184 device_type = "tbi-phy";
190 #address-cells = <1>;
191 #size-cells = <1>;
192 cell-index = <1>;
198 local-mac-address = [ 00 00 00 00 00 00 ];
200 interrupt-parent = <&mpic>;
201 phy-handle = <&phy1>;
204 #address-cells = <1>;
205 #size-cells = <0>;
206 compatible = "fsl,gianfar-tbi";
209 tbi1: tbi-phy@11 {
211 device_type = "tbi-phy";
217 #address-cells = <1>;
218 #size-cells = <1>;
219 cell-index = <2>;
225 local-mac-address = [ 00 00 00 00 00 00 ];
227 interrupt-parent = <&mpic>;
228 phy-handle = <&phy3>;
231 #address-cells = <1>;
232 #size-cells = <0>;
233 compatible = "fsl,gianfar-tbi";
236 tbi2: tbi-phy@11 {
238 device_type = "tbi-phy";
244 cell-index = <0>;
248 clock-frequency = <0>; // should we fill in in uboot?
250 interrupt-parent = <&mpic>;
254 cell-index = <1>;
258 clock-frequency = <0>; // should we fill in in uboot?
260 interrupt-parent = <&mpic>;
264 interrupt-controller;
265 #address-cells = <0>;
266 #interrupt-cells = <2>;
268 device_type = "open-pic";
269 compatible = "chrp,open-pic";
274 #address-cells = <2>;
275 #size-cells = <1>;
276 compatible = "fsl,mpc8540-localbus", "fsl,pq3-localbus",
277 "simple-bus";
279 interrupt-parent = <&mpic>;
285 #address-cells = <1>;
286 #size-cells = <1>;
287 compatible = "cfi-flash";
289 bank-width = <4>;
290 device-width = <2>;
308 label = "u-boot";
310 read-only;
316 #interrupt-cells = <1>;
317 #size-cells = <2>;
318 #address-cells = <3>;
319 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
322 clock-frequency = <66666666>;
323 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
324 interrupt-map = <
336 interrupt-parent = <&mpic>;
338 bus-range = <0 0>;