Lines Matching +full:0 +full:x9000
28 #size-cells = <0>;
30 PowerPC,8555@0 {
32 reg = <0x0>;
35 d-cache-size = <0x8000>; // L1, 32K
36 i-cache-size = <0x8000>; // L1, 32K
37 timebase-frequency = <0>; // 33 MHz, from uboot
38 bus-frequency = <0>; // 166 MHz
39 clock-frequency = <0>; // 825 MHz, from uboot
46 reg = <0x00000000 0x10000000>;
54 ranges = <0x0 0xe0000000 0x100000>;
55 bus-frequency = <0>;
57 ecm-law@0 {
59 reg = <0x0 0x1000>;
65 reg = <0x1000 0x1000>;
72 reg = <0x2000 0x1000>;
79 reg = <0x20000 0x1000>;
81 cache-size = <0x40000>; // L2, 256K
88 #size-cells = <0>;
89 cell-index = <0>;
91 reg = <0x3000 0x100>;
101 reg = <0x21300 0x4>;
102 ranges = <0x0 0x21100 0x200>;
103 cell-index = <0>;
104 dma-channel@0 {
107 reg = <0x0 0x80>;
108 cell-index = <0>;
115 reg = <0x80 0x80>;
123 reg = <0x100 0x80>;
131 reg = <0x180 0x80>;
141 cell-index = <0>;
145 reg = <0x24000 0x1000>;
146 ranges = <0x0 0x24000 0x1000>;
155 #size-cells = <0>;
157 reg = <0x520 0x20>;
162 reg = <0x2>;
167 reg = <0x4>;
170 reg = <0x11>;
183 reg = <0x25000 0x1000>;
184 ranges = <0x0 0x25000 0x1000>;
193 #size-cells = <0>;
195 reg = <0x520 0x20>;
198 reg = <0x11>;
205 cell-index = <0>;
208 reg = <0x4500 0x100>; // reg base, size
209 clock-frequency = <0>; // should we fill in in uboot?
218 reg = <0x4600 0x100>; // reg base, size
219 clock-frequency = <0>; // should we fill in in uboot?
225 compatible = "fsl,sec2.0";
226 reg = <0x30000 0x10000>;
231 fsl,exec-units-mask = <0x7e>;
232 fsl,descriptor-types-mask = <0x01010ebf>;
237 #address-cells = <0>;
239 reg = <0x40000 0x40000>;
248 reg = <0x919c0 0x30>;
254 ranges = <0x0 0x80000 0x10000>;
256 data@0 {
258 reg = <0x0 0x2000 0x9000 0x1000>;
266 reg = <0x919f0 0x10 0x915f0 0x10>;
271 #address-cells = <0>;
275 reg = <0x90c00 0x80>;
282 interrupt-map-mask = <0x1f800 0x0 0x0 0x7>;
285 /* IDSEL 0x10 */
286 0x8000 0x0 0x0 0x1 &mpic 0x0 0x1
287 0x8000 0x0 0x0 0x2 &mpic 0x1 0x1
288 0x8000 0x0 0x0 0x3 &mpic 0x2 0x1
289 0x8000 0x0 0x0 0x4 &mpic 0x3 0x1
291 /* IDSEL 0x11 */
292 0x8800 0x0 0x0 0x1 &mpic 0x0 0x1
293 0x8800 0x0 0x0 0x2 &mpic 0x1 0x1
294 0x8800 0x0 0x0 0x3 &mpic 0x2 0x1
295 0x8800 0x0 0x0 0x4 &mpic 0x3 0x1
297 /* IDSEL 0x12 (Slot 1) */
298 0x9000 0x0 0x0 0x1 &mpic 0x0 0x1
299 0x9000 0x0 0x0 0x2 &mpic 0x1 0x1
300 0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
301 0x9000 0x0 0x0 0x4 &mpic 0x3 0x1
303 /* IDSEL 0x13 (Slot 2) */
304 0x9800 0x0 0x0 0x1 &mpic 0x1 0x1
305 0x9800 0x0 0x0 0x2 &mpic 0x2 0x1
306 0x9800 0x0 0x0 0x3 &mpic 0x3 0x1
307 0x9800 0x0 0x0 0x4 &mpic 0x0 0x1
309 /* IDSEL 0x14 (Slot 3) */
310 0xa000 0x0 0x0 0x1 &mpic 0x2 0x1
311 0xa000 0x0 0x0 0x2 &mpic 0x3 0x1
312 0xa000 0x0 0x0 0x3 &mpic 0x0 0x1
313 0xa000 0x0 0x0 0x4 &mpic 0x1 0x1
315 /* IDSEL 0x15 (Slot 4) */
316 0xa800 0x0 0x0 0x1 &mpic 0x3 0x1
317 0xa800 0x0 0x0 0x2 &mpic 0x0 0x1
318 0xa800 0x0 0x0 0x3 &mpic 0x1 0x1
319 0xa800 0x0 0x0 0x4 &mpic 0x2 0x1
322 /* IDSEL 0x12 (ISA bridge) */
323 0x19000 0x0 0x0 0x1 &mpic 0x0 0x1
324 0x19000 0x0 0x0 0x2 &mpic 0x1 0x1
325 0x19000 0x0 0x0 0x3 &mpic 0x2 0x1
326 0x19000 0x0 0x0 0x4 &mpic 0x3 0x1>;
329 bus-range = <0 0>;
330 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
331 0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
336 reg = <0xe0008000 0x1000>;
343 reg = <0x19000 0x0 0x0 0x0 0x1>;
344 #address-cells = <0>;
353 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
356 /* IDSEL 0x15 */
357 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
358 0xa800 0x0 0x0 0x2 &mpic 0xb 0x1
359 0xa800 0x0 0x0 0x3 &mpic 0xb 0x1
360 0xa800 0x0 0x0 0x4 &mpic 0xb 0x1>;
363 bus-range = <0 0>;
364 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
365 0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
370 reg = <0xe0009000 0x1000>;