Lines Matching +full:dma +full:- +full:ranges
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * STX GP3 - 8560 ADS Device Tree Source
8 /dts-v1/;
12 compatible = "stx,gp3-8560", "stx,gp3";
13 #address-cells = <1>;
14 #size-cells = <1>;
24 #address-cells = <1>;
25 #size-cells = <0>;
30 d-cache-line-size = <32>;
31 i-cache-line-size = <32>;
32 d-cache-size = <32768>;
33 i-cache-size = <32768>;
34 timebase-frequency = <0>;
35 bus-frequency = <0>;
36 clock-frequency = <0>;
37 next-level-cache = <&L2>;
47 #address-cells = <1>;
48 #size-cells = <1>;
50 ranges = <0 0xfdf00000 0x100000>;
51 bus-frequency = <0>;
52 compatible = "fsl,mpc8560-immr", "simple-bus";
54 ecm-law@0 {
55 compatible = "fsl,ecm-law";
57 fsl,num-laws = <8>;
61 compatible = "fsl,mpc8560-ecm", "fsl,ecm";
64 interrupt-parent = <&mpic>;
67 memory-controller@2000 {
68 compatible = "fsl,mpc8540-memory-controller";
70 interrupt-parent = <&mpic>;
74 L2: l2-cache-controller@20000 {
75 compatible = "fsl,mpc8540-l2-cache-controller";
77 cache-line-size = <32>;
78 cache-size = <0x40000>; // L2, 256K
79 interrupt-parent = <&mpic>;
84 #address-cells = <1>;
85 #size-cells = <0>;
86 cell-index = <0>;
87 compatible = "fsl-i2c";
90 interrupt-parent = <&mpic>;
94 dma@21300 {
95 #address-cells = <1>;
96 #size-cells = <1>;
97 compatible = "fsl,mpc8560-dma", "fsl,eloplus-dma";
99 ranges = <0x0 0x21100 0x200>;
100 cell-index = <0>;
101 dma-channel@0 {
102 compatible = "fsl,mpc8560-dma-channel",
103 "fsl,eloplus-dma-channel";
105 cell-index = <0>;
106 interrupt-parent = <&mpic>;
109 dma-channel@80 {
110 compatible = "fsl,mpc8560-dma-channel",
111 "fsl,eloplus-dma-channel";
113 cell-index = <1>;
114 interrupt-parent = <&mpic>;
117 dma-channel@100 {
118 compatible = "fsl,mpc8560-dma-channel",
119 "fsl,eloplus-dma-channel";
121 cell-index = <2>;
122 interrupt-parent = <&mpic>;
125 dma-channel@180 {
126 compatible = "fsl,mpc8560-dma-channel",
127 "fsl,eloplus-dma-channel";
129 cell-index = <3>;
130 interrupt-parent = <&mpic>;
136 #address-cells = <1>;
137 #size-cells = <1>;
138 cell-index = <0>;
143 ranges = <0x0 0x24000 0x1000>;
144 local-mac-address = [ 00 00 00 00 00 00 ];
146 interrupt-parent = <&mpic>;
147 tbi-handle = <&tbi0>;
148 phy-handle = <&phy2>;
151 #address-cells = <1>;
152 #size-cells = <0>;
153 compatible = "fsl,gianfar-mdio";
156 phy2: ethernet-phy@2 {
157 interrupt-parent = <&mpic>;
161 phy4: ethernet-phy@4 {
162 interrupt-parent = <&mpic>;
166 tbi0: tbi-phy@11 {
168 device_type = "tbi-phy";
174 #address-cells = <1>;
175 #size-cells = <1>;
176 cell-index = <1>;
181 ranges = <0x0 0x25000 0x1000>;
182 local-mac-address = [ 00 00 00 00 00 00 ];
184 interrupt-parent = <&mpic>;
185 tbi-handle = <&tbi1>;
186 phy-handle = <&phy4>;
189 #address-cells = <1>;
190 #size-cells = <0>;
191 compatible = "fsl,gianfar-tbi";
194 tbi1: tbi-phy@11 {
196 device_type = "tbi-phy";
202 interrupt-controller;
203 #address-cells = <0>;
204 #interrupt-cells = <2>;
206 compatible = "chrp,open-pic";
207 device_type = "open-pic";
211 #address-cells = <1>;
212 #size-cells = <1>;
213 compatible = "fsl,mpc8560-cpm", "fsl,cpm2", "simple-bus";
215 ranges;
218 #address-cells = <1>;
219 #size-cells = <1>;
220 ranges = <0 0x80000 0x10000>;
223 compatible = "fsl,cpm-muram-data";
229 compatible = "fsl,mpc8560-brg",
230 "fsl,cpm2-brg",
231 "fsl,cpm-brg";
233 clock-frequency = <0>;
237 interrupt-controller;
238 #address-cells = <0>;
239 #interrupt-cells = <2>;
241 interrupt-parent = <&mpic>;
243 compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic";
248 compatible = "fsl,mpc8560-scc-uart",
249 "fsl,cpm2-scc-uart";
251 fsl,cpm-brg = <2>;
252 fsl,cpm-command = <0x4a00000>;
254 interrupt-parent = <&cpmpic>;
260 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
261 interrupt-map = <
287 interrupt-parent = <&mpic>;
289 bus-range = <0 0>;
290 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
292 clock-frequency = <66666666>;
293 #interrupt-cells = <1>;
294 #size-cells = <2>;
295 #address-cells = <3>;
297 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";