Lines Matching +full:reg +full:- +full:names
2 * T2080PCIe-RDB Board Device Tree Source
4 * Copyright 2014 - 2015 Freescale Semiconductor Inc.
14 * names of its contributors may be used to endorse or promote products
35 /include/ "t208xsi-pre.dtsi"
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
46 reg = <0xf 0xfe0c0000 0 0x11000>;
60 phy-handle = <&xg_aq1202_phy3>;
61 phy-connection-type = "xgmii";
65 phy-handle = <&xg_aq1202_phy4>;
66 phy-connection-type = "xgmii";
70 phy-handle = <&rgmii_phy1>;
71 phy-connection-type = "rgmii";
75 phy-handle = <&rgmii_phy2>;
76 phy-connection-type = "rgmii";
80 phy-handle = <&xg_cs4315_phy2>;
81 phy-connection-type = "xgmii";
85 phy-handle = <&xg_cs4315_phy1>;
86 phy-connection-type = "xgmii";
90 rgmii_phy1: ethernet-phy@1 {
91 reg = <0x1>;
93 rgmii_phy2: ethernet-phy@2 {
94 reg = <0x2>;
99 xg_cs4315_phy1: ethernet-phy@c {
100 compatible = "ethernet-phy-id13e5.1002";
101 reg = <0xc>;
104 xg_cs4315_phy2: ethernet-phy@d {
105 compatible = "ethernet-phy-id13e5.1002";
106 reg = <0xd>;
109 xg_aq1202_phy3: ethernet-phy@0 {
110 compatible = "ethernet-phy-ieee802.3-c45";
111 reg = <0x0>;
114 xg_aq1202_phy4: ethernet-phy@1 {
115 compatible = "ethernet-phy-ieee802.3-c45";
116 reg = <0x1>;
122 /include/ "t2080si-post.dtsi"