Lines Matching +full:reg +full:- +full:names
4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
14 * names of its contributors may be used to endorse or promote products
35 /include/ "p5040si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
74 reserved-memory {
75 #address-cells = <2>;
76 #size-cells = <2>;
79 bman_fbpr: bman-fbpr {
83 qman_fqd: qman-fqd {
87 qman_pfdr: qman-pfdr {
97 bportals: bman-portals@ff4000000 {
101 qportals: qman-portals@ff4200000 {
107 reg = <0xf 0xfe000000 0 0x00001000>;
110 #address-cells = <1>;
111 #size-cells = <1>;
112 compatible = "spansion,s25sl12801", "jedec,spi-nor";
113 reg = <0>;
114 spi-max-frequency = <40000000>; /* input clock */
115 partition@u-boot {
116 label = "u-boot";
117 reg = <0x00000000 0x00100000>;
121 reg = <0x00100000 0x00500000>;
125 reg = <0x00600000 0x00100000>;
129 reg = <0x00700000 0x00900000>;
137 reg = <0x51>;
141 reg = <0x52>;
148 reg = <0x68>;
153 reg = <0x40>;
154 shunt-resistor = <1000>;
158 reg = <0x41>;
159 shunt-resistor = <1000>;
163 reg = <0x44>;
164 shunt-resistor = <1000>;
168 reg = <0x45>;
169 shunt-resistor = <1000>;
173 reg = <0x4c>;
179 phy-connection-type = "sgmii";
183 phy-connection-type = "sgmii";
187 phy-connection-type = "sgmii";
191 phy-connection-type = "sgmii";
195 phy-handle = <&phy_rgmii_0>;
196 phy-connection-type = "rgmii";
200 phy-handle = <&phy_xgmii_slot_2>;
201 phy-connection-type = "xgmii";
207 phy-connection-type = "sgmii";
211 phy-connection-type = "sgmii";
215 phy-connection-type = "sgmii";
219 phy-connection-type = "sgmii";
223 phy-handle = <&phy_rgmii_1>;
224 phy-connection-type = "rgmii";
228 phy-handle = <&phy_xgmii_slot_1>;
229 phy-connection-type = "xgmii";
235 reg = <0xf 0xfe124000 0 0x1000>;
241 compatible = "cfi-flash";
242 reg = <0 0 0x08000000>;
243 bank-width = <2>;
244 device-width = <2>;
248 #address-cells = <1>;
249 #size-cells = <1>;
250 compatible = "fsl,elbc-fcm-nand";
251 reg = <0x2 0x0 0x40000>;
254 label = "NAND U-Boot Image";
255 reg = <0x0 0x02000000>;
260 reg = <0x02000000 0x10000000>;
265 reg = <0x12000000 0x08000000>;
270 reg = <0x1a000000 0x04000000>;
275 reg = <0x1e000000 0x01000000>;
280 reg = <0x1f000000 0x01000000>;
284 board-control@3,0 {
285 #address-cells = <1>;
286 #size-cells = <1>;
287 compatible = "fsl,p5040ds-fpga", "fsl,fpga-ngpixis";
288 reg = <3 0 0x40>;
291 mdio-mux-emi1 {
292 #address-cells = <1>;
293 #size-cells = <0>;
294 compatible = "mdio-mux-mmioreg", "mdio-mux";
295 mdio-parent-bus = <&mdio0>;
296 reg = <9 1>;
297 mux-mask = <0x78>;
299 hydra_rg:rgmii-mdio@8 {
300 #address-cells = <1>;
301 #size-cells = <0>;
302 reg = <8>;
305 phy_rgmii_0: ethernet-phy@0 {
306 reg = <0x0>;
309 phy_rgmii_1: ethernet-phy@1 {
310 reg = <0x1>;
314 hydra_sg_slot2: sgmii-mdio@28 {
315 #address-cells = <1>;
316 #size-cells = <0>;
317 reg = <0x28>;
320 phy_sgmii_slot2_1c: ethernet-phy@1c {
321 reg = <0x1c>;
324 phy_sgmii_slot2_1d: ethernet-phy@1d {
325 reg = <0x1d>;
328 phy_sgmii_slot2_1e: ethernet-phy@1e {
329 reg = <0x1e>;
332 phy_sgmii_slot2_1f: ethernet-phy@1f {
333 reg = <0x1f>;
337 hydra_sg_slot3: sgmii-mdio@68 {
338 #address-cells = <1>;
339 #size-cells = <0>;
340 reg = <0x68>;
343 phy_sgmii_slot3_1c: ethernet-phy@1c {
344 reg = <0x1c>;
347 phy_sgmii_slot3_1d: ethernet-phy@1d {
348 reg = <0x1d>;
351 phy_sgmii_slot3_1e: ethernet-phy@1e {
352 reg = <0x1e>;
355 phy_sgmii_slot3_1f: ethernet-phy@1f {
356 reg = <0x1f>;
360 hydra_sg_slot5: sgmii-mdio@38 {
361 #address-cells = <1>;
362 #size-cells = <0>;
363 reg = <0x38>;
366 phy_sgmii_slot5_1c: ethernet-phy@1c {
367 reg = <0x1c>;
370 phy_sgmii_slot5_1d: ethernet-phy@1d {
371 reg = <0x1d>;
374 phy_sgmii_slot5_1e: ethernet-phy@1e {
375 reg = <0x1e>;
378 phy_sgmii_slot5_1f: ethernet-phy@1f {
379 reg = <0x1f>;
382 hydra_sg_slot6: sgmii-mdio@48 {
383 #address-cells = <1>;
384 #size-cells = <0>;
385 reg = <0x48>;
388 phy_sgmii_slot6_1c: ethernet-phy@1c {
389 reg = <0x1c>;
392 phy_sgmii_slot6_1d: ethernet-phy@1d {
393 reg = <0x1d>;
396 phy_sgmii_slot6_1e: ethernet-phy@1e {
397 reg = <0x1e>;
400 phy_sgmii_slot6_1f: ethernet-phy@1f {
401 reg = <0x1f>;
406 mdio-mux-emi2 {
407 #address-cells = <1>;
408 #size-cells = <0>;
409 compatible = "mdio-mux-mmioreg", "mdio-mux";
410 mdio-parent-bus = <&xmdio0>;
411 reg = <9 1>;
412 mux-mask = <0x06>;
414 hydra_xg_slot1: hydra-xg-slot1@0 {
415 #address-cells = <1>;
416 #size-cells = <0>;
417 reg = <0>;
420 phy_xgmii_slot_1: ethernet-phy@0 {
421 compatible = "ethernet-phy-ieee802.3-c45";
422 reg = <4>;
426 hydra_xg_slot2: hydra-xg-slot2@2 {
427 #address-cells = <1>;
428 #size-cells = <0>;
429 reg = <2>;
431 phy_xgmii_slot_2: ethernet-phy@4 {
432 compatible = "ethernet-phy-ieee802.3-c45";
433 reg = <0>;
441 reg = <0xf 0xfe200000 0 0x1000>;
456 reg = <0xf 0xfe201000 0 0x1000>;
471 reg = <0xf 0xfe202000 0 0x1000>;
486 /include/ "p5040si-post.dtsi"