dts/fsl/mpc8548cds.dtsi

2  * MPC8548CDS Device Tree Source stub (no addresses or top-level ranges)
14  *       names of its contributors may be used to endorse or promote products
37 		#address-cells = <1>;
38 		#size-cells = <1>;
39 		compatible = "cfi-flash";
40 		reg = <0x0 0x0 0x01000000>;
41 		bank-width = <2>;
42 		device-width = <2>;
45 			reg = <0x0 0x0b00000>;
46 			label = "ramdisk-nor";
50 			reg = <0x0b00000 0x0400000>;
51 			label = "kernel-nor";
55 			reg = <0x0f00000 0x060000>;
56 			label = "dtb-nor";
60 			reg = <0x0f60000 0x020000>;
61 			label = "env-nor";
62 			read-only;
66 			reg = <0x0f80000 0x080000>;
67 			label = "u-boot-nor";
68 			read-only;
72 	board-control@1,0 {
73 		compatible = "fsl,mpc8548cds-fpga";
74 		reg = <0x1 0x0 0x1000>;
82 			reg = <0x50>;
87 			reg = <0x56>;
92 			reg = <0x57>;
99 			reg = <0x50>;
104 		tbi-handle = <&tbi0>;
105 		phy-handle = <&phy0>;
109 		phy0: ethernet-phy@0 {
111 			reg = <0x0>;
113 		phy1: ethernet-phy@1 {
115 			reg = <0x1>;
117 		phy2: ethernet-phy@2 {
119 			reg = <0x2>;
121 		phy3: ethernet-phy@3 {
123 			reg = <0x3>;
125 		tbi0: tbi-phy@11 {
126 			reg = <0x11>;
127 			device_type = "tbi-phy";
132 		tbi-handle = <&tbi1>;
133 		phy-handle = <&phy1>;
137 		tbi1: tbi-phy@11 {
138 			reg = <0x11>;
139 			device_type = "tbi-phy";
144 		tbi-handle = <&tbi2>;
145 		phy-handle = <&phy2>;
149 		tbi2: tbi-phy@11 {
150 			reg = <0x11>;
151 			device_type = "tbi-phy";
156 		tbi-handle = <&tbi3>;
157 		phy-handle = <&phy3>;
161 		tbi3: tbi-phy@11 {
162 			reg = <0x11>;
163 			device_type = "tbi-phy";
169 	interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
170 	interrupt-map = <
232 		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
233 		interrupt-map = <
262 		reg = <0xe000 0x0 0x0 0x0 0x0>;
263 		#interrupt-cells = <1>;
264 		#size-cells = <2>;
265 		#address-cells = <3>;
272 		clock-frequency = <33333333>;
276 			#interrupt-cells = <2>;
277 			#size-cells = <1>;
278 			#address-cells = <2>;
279 			reg = <0x2000 0x0 0x0 0x0 0x0>;
281 			interrupt-parent = <&i8259>;
283 			i8259: interrupt-controller@20 {
284 				interrupt-controller;
285 				device_type = "interrupt-controller";
286 				reg = <0x1 0x20 0x2
289 				#address-cells = <0>;
290 				#interrupt-cells = <2>;
293 				interrupt-parent = <&mpic>;
298 				reg = <0x1 0x70 0x2>;