Lines Matching +full:reg +full:- +full:names
4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
14 * names of its contributors may be used to endorse or promote products
35 /dts-v1/;
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
72 #address-cells = <1>;
73 #size-cells = <0>;
77 reg = <0 1>;
79 next-level-cache = <&L2_1>;
80 fsl,portid-mapping = <0x80000000>;
84 reg = <2 3>;
86 next-level-cache = <&L2_1>;
87 fsl,portid-mapping = <0x80000000>;
91 reg = <4 5>;
93 next-level-cache = <&L2_1>;
94 fsl,portid-mapping = <0x80000000>;
98 reg = <6 7>;
100 next-level-cache = <&L2_1>;
101 fsl,portid-mapping = <0x80000000>;