Lines Matching +full:pdc +full:- +full:global
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Linux/PA-RISC Project (http://www.parisc-linux.org/)
8 * Copyright (C) 2000 Hewlett-Packard (John Marvin)
9 * Copyright (C) 1999 Hewlett-Packard (Frank Rowand)
12 #include <asm/asm-offsets.h>
15 * - handle in assembly and use shadowed registers only
16 * - save registers to kernel stack and handle in assembly or C */
41 addil L%(PAGE_SIZE << (PGD_ALLOC_ORDER - 1)),\reg
52 extrd,u \spc,(64 - (SPACEID_SHIFT)),32,\prot
98 * to use a non-shadowed register to carry the value over
103 * be a non-shadowed register so that it survives the rfir.
118 LDREG TI_TASK(%r9), %r1 /* thread_info -> task_struct */
191 * itlb miss interruption handler (parisc 1.1 - 32 bit)
222 * naitlb miss interruption handler (parisc 1.1 - 32 bit)
254 * dtlb miss interruption handler (parisc 1.1 - 32 bit)
285 /* nadtlb miss interruption handler (parisc 1.1 - 32 bit) */
314 * dirty bit trap interruption handler (parisc 1.1 - 32 bit)
370 spc - The space we saw the fault with.
371 tmp - The place to store the current space.
372 fault - Function to call on failure.
389 /* Look up a PTE in a 2-Level scheme (faulting at each
397 extru \va,31-ASM_PMD_SHIFT,ASM_BITS_PER_PMD,\index
400 extrd,u \va,63-ASM_PGDIR_SHIFT,ASM_BITS_PER_PGD,\index
403 extru \va,31-ASM_PGDIR_SHIFT,32-ASM_PGDIR_SHIFT,\index
405 extru \va,31-ASM_PGDIR_SHIFT,ASM_BITS_PER_PGD,\index
415 extru \va,31-PAGE_SHIFT,ASM_BITS_PER_PTE,\index
420 /* Look up PTE in a 3-Level scheme.
431 #if CONFIG_PGTABLE_LEVELS == 3 /* we might have a 2-Level scheme, e.g. with 16kb page size */
432 extrd,u \va,63-ASM_PGDIR_SHIFT,ASM_BITS_PER_PGD,\index
433 extrd,u,*= \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
435 extrd,u,*= \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
437 extrd,u,*= \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
439 extrd,u,*= \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
441 extrd,u,*<> \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
507 * - 38 to 52-bit Physical Page Number
508 * - 12 to 26-bit page offset
512 #define PAGE_ADD_SHIFT (PAGE_SHIFT-12)
513 #define PAGE_ADD_HUGE_SHIFT (REAL_HPAGE_SHIFT-12)
519 extrd,u \tmp,(63-ASM_PFN_PTE_SHIFT)+(63-58)+PAGE_ADD_SHIFT,\
520 64-PAGE_SHIFT-PAGE_ADD_SHIFT,\pte
523 (63-58)+PAGE_ADD_SHIFT,\pte
526 (63-58)+PAGE_ADD_HUGE_SHIFT,\pte
528 extrd,u \pte,(63-ASM_PFN_PTE_SHIFT)+(63-58)+PAGE_ADD_SHIFT,\
529 64-PAGE_SHIFT-PAGE_ADD_SHIFT,\pte
531 (63-58)+PAGE_ADD_SHIFT,\pte
540 * T <-> _PAGE_REFTRAP
541 * D <-> _PAGE_DIRTY
542 * B <-> _PAGE_DMB (memory break)
546 * See 3-14 of the parisc 2.0 manual
567 * (that means T-class is NOT supported) and the memory controllers
593 SHRREG \pte,(ASM_PFN_PTE_SHIFT-(31-26)),\pte
612 * the from tlb entry (or nothing if only a to entry---for
774 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30), %r1
793 STREG %r2, -RP_OFFSET(%r30)
814 LDREG -RP_OFFSET(%r30), %r2
837 LDREG TI_TASK(%r16), %r16 /* thread_info -> task_struct */
883 bb,<,n %r19,31-TIF_NEED_RESCHED,intr_do_resched /* forward */
908 ldo -16(%r30),%r29 /* Reference param save area */
967 ldo -16(%r30),%r29 /* Reference param save area */
989 /* current_thread_info()->preempt_count */
997 bb,<,n %r20, 31 - PSW_SM_I, intr_restore
1034 ldo -16(%r30),%r29 /* Reference param save area */
1083 /* Revisit when we have 64-bit code above 4Gb */
1114 ldo -16(%r30),%r29 /* Reference param save area */
1335 * Non access misses can be caused by fdc,fic,pdc,lpa,probe and
1344 * emulate fdc,fic,pdc,probew,prober instructions whose base
1352 Checks for fdc,fdce,pdc,"fic,4f",prober,probeir,probew, probeiw */
1354 /* Checks for fdc,fdce,pdc,"fic,4f" only */
1361 cmpib,COND(=),n -1,%r1,nadtlb_fault /* have to use slow path */
1365 cmpib,COND(=),n -1,%r1,nadtlb_fault /* have to use slow path */
1387 WARNING: USE ONLY NON-SHADOW REGISTERS WITH PROBE INSN!
1388 THE SLOW-PATH EMULATION HAS NOT BEEN WRITTEN YET.
1397 cmpib,COND(=),n -1,%r1,nadtlb_fault /* have to use slow path */
1668 %r3 - %r18 preserved by C code (saved by signal code)
1669 %r19 - %r20 saved in PT_REGS by gateway page
1670 %r21 - %r22 non-standard syscall args
1672 %r23 - %r26 arg3-arg0, saved in PT_REGS by gateway page
1673 %r27 - %r30 saved in PT_REGS by gateway page
1679 %fr0 - %fr3 status/exception, not preserved
1680 %fr4 - %fr7 arguments
1681 %fr8 - %fr11 not preserved by C code
1682 %fr12 - %fr21 preserved by C code
1683 %fr22 - %fr31 not preserved by C code
1726 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30), %r1
1746 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30), %r1
1757 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r26
1760 STREG %r2, -RP_OFFSET(%r30)
1764 ldo -16(%r30),%r29 /* Reference param save area */
1770 ldo -FRAME_SIZE(%r30), %r30
1771 LDREG -RP_OFFSET(%r30), %r2
1774 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1807 LDREG TI_FLAGS-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r19 /* long */
1808 bb,<,n %r19, 31-TIF_NEED_RESCHED, syscall_do_resched /* forward */
1812 LDREG TI_FLAGS-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r19
1818 /* Save callee-save registers (for sigcontext).
1823 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1828 ldo -16(%r30),%r29 /* Reference param save area */
1834 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1841 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1903 ldo -1(%r0),%r2 /* Set recovery cntr to -1 */
1907 depi -1,13,1,%r20 /* C, Q, D, and I bits */
1911 * numbers in asm-offsets.c */
1915 depi -1,27,1,%r20 /* R bit */
1919 depi -1,7,1,%r20 /* T bit */
1938 * We could make this more efficient by not saving r3-r18, but
1981 ldo -16(%r30),%r29 /* Reference param save area */
2015 .dword 0 /* code in head.S puts value of global gp here */
2028 .global ftrace_caller
2030 STREG %r3, -FTRACE_FRAME_SIZE+1*REG_SZ(%sp)
2031 ldo -FTRACE_FRAME_SIZE(%sp), %r3
2032 STREG %rp, -RP_OFFSET(%r3)
2049 ldo -16(%sp),%r29
2053 ldo -8(%r25), %r25
2058 LDREG -RP_OFFSET(%r3), %rp
2075 LDREGM -FTRACE_FRAME_SIZE(%sp), %r1
2077 ldo -4(%r1), %r1
2086 .global ftrace_regs_caller
2088 ldo -FTRACE_FRAME_SIZE(%sp), %r1
2089 STREG %rp, -RP_OFFSET(%r1)
2128 LDREG -FTRACE_FRAME_SIZE-PT_SZ_ALGN(%sp), %r25
2129 ldo -8(%r25), %r25
2130 ldo -FTRACE_FRAME_SIZE(%r1), %arg2
2134 ldo -PT_SZ_ALGN(%sp), %r1
2170 ldo -PT_SZ_ALGN(%sp), %sp
2171 LDREGM -FTRACE_FRAME_SIZE(%sp), %r1
2173 ldo -4(%r1), %r1
2187 STREG %r0,-RP_OFFSET(%sp) /* store 0 as %rp */
2202 ldo -16(%sp),%ret1 /* Reference param save area */
2221 LDREGM -FRAME_SIZE(%sp),%r3
2244 STREG %rp, -FRAME_SIZE-RP_OFFSET(%sp)
2248 STREG %r1, -FRAME_SIZE-REG_SZ(%sp)
2249 LDREG -FRAME_SIZE-RP_OFFSET(%sp), %rp
2251 LDREG -FRAME_SIZE-REG_SZ(%sp), %sp
2254 STREG %r1, -FRAME_SIZE-REG_SZ(%sp)
2255 STREG %rp, -FRAME_SIZE-RP_OFFSET(%sp)
2263 LDREG -FRAME_SIZE-RP_OFFSET(%sp), %rp
2265 LDREG -FRAME_SIZE-REG_SZ(%sp), %sp
2276 * registers we put a -1 into r1 to indicate that the register
2278 * a -1 in it, but that is OK, it just means that we will have
2285 bv %r0(%r25) /* r1 - shadowed */
2286 ldi -1,%r1
2299 bv %r0(%r25) /* r8 - shadowed */
2300 ldi -1,%r1
2301 bv %r0(%r25) /* r9 - shadowed */
2302 ldi -1,%r1
2315 bv %r0(%r25) /* r16 - shadowed */
2316 ldi -1,%r1
2317 bv %r0(%r25) /* r17 - shadowed */
2318 ldi -1,%r1
2331 bv %r0(%r25) /* r24 - shadowed */
2332 ldi -1,%r1
2333 bv %r0(%r25) /* r25 - shadowed */
2334 ldi -1,%r1