6  * Copyright (C) 1999-2006 Helge Deller <deller@gmx.de> (07-13-1999)
10  * Cache and TLB management
42 /* On some machines (i.e., ones with the Merced bus), there can be
44  * by software. We need a spinlock around all TLB flushes to ensure
99 	    test_bit(PG_dcache_dirty, &page->flags)) {  in update_mmu_cache()
101 		clear_bit(PG_dcache_dirty, &page->flags);  in update_mmu_cache()
111 	seq_printf(m, "I-cache\t\t: %ld KB\n",   in show_cache_info()
114 		snprintf(buf, 32, "%lu-way associative", cache_info.dc_loop);  in show_cache_info()
115 	seq_printf(m, "D-cache\t\t: %ld KB (%s%s, %s)\n",  in show_cache_info()
118 		(cache_info.dc_conf.cc_sh ? ", shared I/D":""),  in show_cache_info()
123 		cache_info.dt_conf.tc_sh ? " - shared with ITLB":""  in show_cache_info()
127 	/* BTLB - Block TLB */  in show_cache_info()
133 		"BTLB fix-entr.\t: %d instruction, %d data (%d combined)\n"  in show_cache_info()
134 		"BTLB var-entr.\t: %d instruction, %d data (%d combined)\n",  in show_cache_info()
214 	printk("D-TLB conf: sh %d page %d cst %d aid %d sr %d\n",  in parisc_cache_init()
221 	printk("I-TLB conf: sh %d page %d cst %d aid %d sr %d\n",  in parisc_cache_init()
232 			printk(KERN_WARNING "Unexpected TLB configuration. "  in parisc_cache_init()
233 			"Will flush I/D separately (could be optimized).\n");  in parisc_cache_init()
239 	 *	(1 << (cc_block-1)) * (cc_line << (4 + cnf.cc_shift))  in parisc_cache_init()
241 	 * http://lists.parisc-linux.org/pipermail/parisc-linux/2004-June/023625.html  in parisc_cache_init()
242 	 * http://lists.parisc-linux.org/pipermail/parisc-linux/2004-June/023671.html  in parisc_cache_init()
259 		panic("SMP kernel required to avoid non-equivalent aliasing");  in parisc_cache_init()
308 	if (vma->vm_flags & VM_EXEC)  in __flush_cache_page()
319 	if (vma->vm_flags & VM_EXEC)  in __purge_cache_page()
333 		set_bit(PG_dcache_dirty, &page->flags);  in flush_dcache_page()
342 	pgoff = page->index;  in flush_dcache_page()
350 	vma_interval_tree_foreach(mpnt, &mapping->i_mmap, pgoff, pgoff) {  in flush_dcache_page()
351 		offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT;  in flush_dcache_page()
352 		addr = mpnt->vm_start + offset;  in flush_dcache_page()
354 		/* The TLB is the engine of coherence on parisc: The  in flush_dcache_page()
355 		 * CPU is entitled to speculate any page with a TLB  in flush_dcache_page()
358 		 * This guarantees that the page is no-longer in the  in flush_dcache_page()
364 		if (old_addr == 0 || (old_addr & (SHM_COLOUR - 1))  in flush_dcache_page()
365 				      != (addr & (SHM_COLOUR - 1))) {  in flush_dcache_page()
368 …printk(KERN_ERR "INEQUIVALENT ALIASES 0x%lx and 0x%lx in file %pD\n", old_addr, addr, mpnt->vm_fil…  in flush_dcache_page()
385 #define FLUSH_TLB_THRESHOLD (16*1024) /* 16 KiB minimum TLB threshold */
391 	unsigned long size;  in parisc_setup_cache_timing()  local
396 	alltime = mfctl(16) - alltime;  in parisc_setup_cache_timing()
398 	size = (unsigned long)(_end - _text);  in parisc_setup_cache_timing()
400 	flush_kernel_dcache_range((unsigned long)_text, size);  in parisc_setup_cache_timing()
401 	rangetime = mfctl(16) - rangetime;  in parisc_setup_cache_timing()
404 		alltime, size, rangetime);  in parisc_setup_cache_timing()
406 	threshold = L1_CACHE_ALIGN(size * alltime / rangetime);  in parisc_setup_cache_timing()
414 	/* calculate TLB flush threshold */  in parisc_setup_cache_timing()
416 	/* On SMP machines, skip the TLB measure of kernel text which  in parisc_setup_cache_timing()
425 	size = (unsigned long)_end - (unsigned long)_text;  in parisc_setup_cache_timing()
428 	rangetime = mfctl(16) - rangetime;  in parisc_setup_cache_timing()
432 	alltime = mfctl(16) - alltime;  in parisc_setup_cache_timing()
434 	printk(KERN_INFO "Whole TLB flush %lu cycles, Range flush %lu bytes %lu cycles\n",  in parisc_setup_cache_timing()
435 		alltime, size, rangetime);  in parisc_setup_cache_timing()
437 	threshold = PAGE_ALIGN((num_online_cpus() * size * alltime) / rangetime);  in parisc_setup_cache_timing()
438 	printk(KERN_INFO "Calculated TLB flush threshold %lu KiB\n",  in parisc_setup_cache_timing()
447 	printk(KERN_INFO "TLB flush threshold set to %lu KiB\n",  in parisc_setup_cache_timing()
490 	    end - start >= parisc_tlb_flush_threshold) {  in __flush_tlb_range()
495 	/* Purge TLB entries for small ranges using the pdtlb and  in __flush_tlb_range()
524 	for (vma = mm->mmap; vma; vma = vma->vm_next)  in mm_total_size()
525 		usize += vma->vm_end - vma->vm_start;  in mm_total_size()
556 		if (mm->context)  in flush_cache_mm()
562 	if (mm->context == mfsp(3)) {  in flush_cache_mm()
563 		for (vma = mm->mmap; vma; vma = vma->vm_next) {  in flush_cache_mm()
564 			flush_user_dcache_range_asm(vma->vm_start, vma->vm_end);  in flush_cache_mm()
565 			if (vma->vm_flags & VM_EXEC)  in flush_cache_mm()
566 				flush_user_icache_range_asm(vma->vm_start, vma->vm_end);  in flush_cache_mm()
567 			flush_tlb_range(vma, vma->vm_start, vma->vm_end);  in flush_cache_mm()
572 	pgd = mm->pgd;  in flush_cache_mm()
573 	for (vma = mm->mmap; vma; vma = vma->vm_next) {  in flush_cache_mm()
576 		for (addr = vma->vm_start; addr < vma->vm_end;  in flush_cache_mm()
585 			if (unlikely(mm->context)) {  in flush_cache_mm()
602 	    end - start >= parisc_cache_flush_threshold) {  in flush_cache_range()
603 		if (vma->vm_mm->context)  in flush_cache_range()
609 	if (vma->vm_mm->context == mfsp(3)) {  in flush_cache_range()
611 		if (vma->vm_flags & VM_EXEC)  in flush_cache_range()
617 	pgd = vma->vm_mm->pgd;  in flush_cache_range()
618 	for (addr = vma->vm_start; addr < vma->vm_end; addr += PAGE_SIZE) {  in flush_cache_range()
625 			if (unlikely(vma->vm_mm->context)) {  in flush_cache_range()
639 		if (likely(vma->vm_mm->context)) {  in flush_cache_page()
648 void flush_kernel_vmap_range(void *vaddr, int size)  in flush_kernel_vmap_range()  argument
651 	unsigned long end = start + size;  in flush_kernel_vmap_range()
654 	    (unsigned long)size >= parisc_cache_flush_threshold) {  in flush_kernel_vmap_range()
665 void invalidate_kernel_vmap_range(void *vaddr, int size)  in invalidate_kernel_vmap_range()  argument
668 	unsigned long end = start + size;  in invalidate_kernel_vmap_range()
671 	    (unsigned long)size >= parisc_cache_flush_threshold) {  in invalidate_kernel_vmap_range()