Lines Matching +full:0 +full:x308
47 #if DELAYED_RESOURCE_CNT > 0
56 #define SBA_SEARCH_SAMPLE 0x100
89 #define ASTRO_RUNWAY_PORT 0x582
90 #define IKE_MERCED_PORT 0x803
91 #define REO_MERCED_PORT 0x804
92 #define REOG_MERCED_PORT 0x805
93 #define PLUTO_MCKINLEY_PORT 0x880
111 #define SBA_PDIR_VALID_BIT 0x8000000000000000ULL
113 #define SBA_AGPGART_COOKIE 0x0000badbadc0ffeeULL
115 #define SBA_FUNC_ID 0x0000 /* function id */
116 #define SBA_FCLASS 0x0008 /* function class, bist, header, rev... */
125 #define IOC_CTRL 0x8 /* IOC_CTRL offset */
126 #define IOC_CTRL_TC (1 << 0) /* TOC Enable */
135 ** Offsets into MBIB (Function 0 on Ike and hopefully Astro)
138 #define LMMIO_DIRECT0_BASE 0x300
139 #define LMMIO_DIRECT0_MASK 0x308
140 #define LMMIO_DIRECT0_ROUTE 0x310
142 #define LMMIO_DIST_BASE 0x360
143 #define LMMIO_DIST_MASK 0x368
144 #define LMMIO_DIST_ROUTE 0x370
146 #define IOS_DIST_BASE 0x390
147 #define IOS_DIST_MASK 0x398
148 #define IOS_DIST_ROUTE 0x3A0
150 #define IOS_DIRECT_BASE 0x3C0
151 #define IOS_DIRECT_MASK 0x3C8
152 #define IOS_DIRECT_ROUTE 0x3D0
157 #define ROPE0_CTL 0x200 /* "regbus pci0" */
158 #define ROPE1_CTL 0x208
159 #define ROPE2_CTL 0x210
160 #define ROPE3_CTL 0x218
161 #define ROPE4_CTL 0x220
162 #define ROPE5_CTL 0x228
163 #define ROPE6_CTL 0x230
164 #define ROPE7_CTL 0x238
166 #define IOC_ROPE0_CFG 0x500 /* pluto only */
167 #define IOC_ROPE_AO 0x10 /* Allow "Relaxed Ordering" */
169 #define HF_ENABLE 0x40
171 #define IOC_IBASE 0x300 /* IO TLB */
172 #define IOC_IMASK 0x308
173 #define IOC_PCOM 0x310
174 #define IOC_TCNFG 0x318
175 #define IOC_PDIR_BASE 0x320
192 #define SBA_PERF_CFG 0x708 /* Performance Counter stuff */
193 #define SBA_PERF_MASK1 0x718
194 #define SBA_PERF_MASK2 0x730
200 #define SBA_PERF_CNT1 0x200
201 #define SBA_PERF_CNT2 0x208
202 #define SBA_PERF_CNT3 0x210
221 #define ELROY_HVERS 0x782
222 #define MERCURY_HVERS 0x783
223 #define QUICKSILVER_HVERS 0x784
240 bus_mode = readl(hpa + 0x0620); in agp_mode_mercury()
244 return 0; in agp_mode_mercury()
258 #define LBA_FUNC_ID 0x0000 /* function id */
259 #define LBA_FCLASS 0x0008 /* function class, bist, header, rev... */
260 #define LBA_CAPABLE 0x0030 /* capabilities register */
262 #define LBA_PCI_CFG_ADDR 0x0040 /* poke CFG address here */
263 #define LBA_PCI_CFG_DATA 0x0048 /* read or write data here */
265 #define LBA_PMC_MTLT 0x0050 /* Firmware sets this - read only. */
266 #define LBA_FW_SCRATCH 0x0058 /* Firmware writes the PCI bus number here. */
267 #define LBA_ERROR_ADDR 0x0070 /* On error, address gets logged here */
269 #define LBA_ARB_MASK 0x0080 /* bit 0 enable arbitration. PAT/PDC enables */
270 #define LBA_ARB_PRI 0x0088 /* firmware sets this. */
271 #define LBA_ARB_MODE 0x0090 /* firmware sets this. */
272 #define LBA_ARB_MTLT 0x0098 /* firmware sets this. */
274 #define LBA_MOD_ID 0x0100 /* Module ID. PDC_PAT_CELL reports 4 */
276 #define LBA_STAT_CTL 0x0108 /* Status & Control */
277 #define LBA_BUS_RESET 0x01 /* Deassert PCI Bus Reset Signal */
278 #define CLEAR_ERRLOG 0x10 /* "Clear Error Log" cmd */
279 #define CLEAR_ERRLOG_ENABLE 0x20 /* "Clear Error Log" Enable */
280 #define HF_ENABLE 0x40 /* enable HF mode (default is -1 mode) */
282 #define LBA_LMMIO_BASE 0x0200 /* < 4GB I/O address range */
283 #define LBA_LMMIO_MASK 0x0208
285 #define LBA_GMMIO_BASE 0x0210 /* > 4GB I/O address range */
286 #define LBA_GMMIO_MASK 0x0218
288 #define LBA_WLMMIO_BASE 0x0220 /* All < 4GB ranges under the same *SBA* */
289 #define LBA_WLMMIO_MASK 0x0228
291 #define LBA_WGMMIO_BASE 0x0230 /* All > 4GB ranges under the same *SBA* */
292 #define LBA_WGMMIO_MASK 0x0238
294 #define LBA_IOS_BASE 0x0240 /* I/O port space for this LBA */
295 #define LBA_IOS_MASK 0x0248
297 #define LBA_ELMMIO_BASE 0x0250 /* Extra LMMIO range */
298 #define LBA_ELMMIO_MASK 0x0258
300 #define LBA_EIOS_BASE 0x0260 /* Extra I/O port space */
301 #define LBA_EIOS_MASK 0x0268
303 #define LBA_GLOBAL_MASK 0x0270 /* Mercury only: Global Address Mask */
304 #define LBA_DMA_CTL 0x0278 /* firmware sets this */
306 #define LBA_IBASE 0x0300 /* SBA DMA support */
307 #define LBA_IMASK 0x0308
310 #define LBA_HINT_CFG 0x0310
311 #define LBA_HINT_BASE 0x0380 /* 14 registers at every 8 bytes. */
313 #define LBA_BUS_MODE 0x0620
316 #define LBA_ERROR_CONFIG 0x0680
317 #define LBA_SMART_MODE 0x20
318 #define LBA_ERROR_STATUS 0x0688
319 #define LBA_ROPE_CTL 0x06A0
321 #define LBA_IOSAPIC_BASE 0x800 /* Offset of IRQ logic */