Lines Matching +full:can +full:- +full:disable

1 # SPDX-License-Identifier: GPL-2.0-only
26 	  Say Y here to enable the lazy FPU scheme. The lazy FPU scheme can
38 	  this feature can enhance the precision for tininess number.
50 	  A set of Zero-Overhead Loop mechanism is provided to reduce the
51 	  instruction fetch and execution overhead of loop-control instructions.
53 	  You don't need to save these registers if you can make sure your user
75 	  if its cache way size is larger than page size. You can specify the
102 	prompt "Paging -- page size "
111 	bool "Disable I-Cache"
113 	  Say Y here to disable the processor instruction cache. Unless
117 	bool "Disable D-Cache"
119 	  Say Y here to disable the processor data cache. Unless
123 	bool "Force write through D-cache"
133 	  Say Y here to enable write-back memory with no-write-allocation policy.
142 	  address divisible by 4. On 32-bit Andes processors, these non-aligned
144 	  here, which has a severe performance impact. With an IP-only
152 	  Andes processors load/store world/half-word instructions can access
154 	  Check exceptions. With an IP-only configuration it is safe to say N,
165 	  memory can be "permanently mapped" by the kernel. The physical
186 	  Only when CPU_VER.REV >= 0x09 can support.