Lines Matching +full:lock +full:- +full:offset
1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2001-2002 MontaVista Software Inc.
7 * Copyright (C) 2003-2006 Yoichi Yuasa <yuasa@linux-mips.org>
12 * - New creation, NEC VR4122 and VR4131 are supported.
13 * - Added support for NEC VR4111 and VR4121.
15 * Yoichi Yuasa <yuasa@linux-mips.org>
16 * - Coped with INTASSIGN of NEC VR4133.
84 #define SYSINT1_IRQ_TO_PIN(x) ((x) - SYSINT1_IRQ_BASE) /* Pin 0-15 */
85 #define SYSINT2_IRQ_TO_PIN(x) ((x) - SYSINT2_IRQ_BASE) /* Pin 0-15 */
87 #define INT_TO_IRQ(x) ((x) + 2) /* Int0-4 -> IRQ2-6 */
89 #define icu1_read(offset) readw(icu1_base + (offset)) argument
90 #define icu1_write(offset, value) writew((value), icu1_base + (offset)) argument
92 #define icu2_read(offset) readw(icu2_base + (offset)) argument
93 #define icu2_write(offset, value) writew((value), icu2_base + (offset)) argument
98 static inline uint16_t icu1_set(uint8_t offset, uint16_t set) in icu1_set() argument
102 data = icu1_read(offset); in icu1_set()
104 icu1_write(offset, data); in icu1_set()
109 static inline uint16_t icu1_clear(uint8_t offset, uint16_t clear) in icu1_clear() argument
113 data = icu1_read(offset); in icu1_clear()
115 icu1_write(offset, data); in icu1_clear()
120 static inline uint16_t icu2_set(uint8_t offset, uint16_t set) in icu2_set() argument
124 data = icu2_read(offset); in icu2_set()
126 icu2_write(offset, data); in icu2_set()
131 static inline uint16_t icu2_clear(uint8_t offset, uint16_t clear) in icu2_clear() argument
135 data = icu2_read(offset); in icu2_clear()
137 icu2_write(offset, data); in icu2_clear()
149 raw_spin_lock_irqsave(&desc->lock, flags); in vr41xx_enable_piuint()
151 raw_spin_unlock_irqrestore(&desc->lock, flags); in vr41xx_enable_piuint()
164 raw_spin_lock_irqsave(&desc->lock, flags); in vr41xx_disable_piuint()
166 raw_spin_unlock_irqrestore(&desc->lock, flags); in vr41xx_disable_piuint()
179 raw_spin_lock_irqsave(&desc->lock, flags); in vr41xx_enable_aiuint()
181 raw_spin_unlock_irqrestore(&desc->lock, flags); in vr41xx_enable_aiuint()
194 raw_spin_lock_irqsave(&desc->lock, flags); in vr41xx_disable_aiuint()
196 raw_spin_unlock_irqrestore(&desc->lock, flags); in vr41xx_disable_aiuint()
209 raw_spin_lock_irqsave(&desc->lock, flags); in vr41xx_enable_kiuint()
211 raw_spin_unlock_irqrestore(&desc->lock, flags); in vr41xx_enable_kiuint()
224 raw_spin_lock_irqsave(&desc->lock, flags); in vr41xx_disable_kiuint()
226 raw_spin_unlock_irqrestore(&desc->lock, flags); in vr41xx_disable_kiuint()
237 raw_spin_lock_irqsave(&desc->lock, flags); in vr41xx_enable_macint()
239 raw_spin_unlock_irqrestore(&desc->lock, flags); in vr41xx_enable_macint()
249 raw_spin_lock_irqsave(&desc->lock, flags); in vr41xx_disable_macint()
251 raw_spin_unlock_irqrestore(&desc->lock, flags); in vr41xx_disable_macint()
261 raw_spin_lock_irqsave(&desc->lock, flags); in vr41xx_enable_dsiuint()
263 raw_spin_unlock_irqrestore(&desc->lock, flags); in vr41xx_enable_dsiuint()
273 raw_spin_lock_irqsave(&desc->lock, flags); in vr41xx_disable_dsiuint()
275 raw_spin_unlock_irqrestore(&desc->lock, flags); in vr41xx_disable_dsiuint()
285 raw_spin_lock_irqsave(&desc->lock, flags); in vr41xx_enable_firint()
287 raw_spin_unlock_irqrestore(&desc->lock, flags); in vr41xx_enable_firint()
297 raw_spin_lock_irqsave(&desc->lock, flags); in vr41xx_disable_firint()
299 raw_spin_unlock_irqrestore(&desc->lock, flags); in vr41xx_disable_firint()
312 raw_spin_lock_irqsave(&desc->lock, flags); in vr41xx_enable_pciint()
314 raw_spin_unlock_irqrestore(&desc->lock, flags); in vr41xx_enable_pciint()
328 raw_spin_lock_irqsave(&desc->lock, flags); in vr41xx_disable_pciint()
330 raw_spin_unlock_irqrestore(&desc->lock, flags); in vr41xx_disable_pciint()
344 raw_spin_lock_irqsave(&desc->lock, flags); in vr41xx_enable_scuint()
346 raw_spin_unlock_irqrestore(&desc->lock, flags); in vr41xx_enable_scuint()
360 raw_spin_lock_irqsave(&desc->lock, flags); in vr41xx_disable_scuint()
362 raw_spin_unlock_irqrestore(&desc->lock, flags); in vr41xx_disable_scuint()
376 raw_spin_lock_irqsave(&desc->lock, flags); in vr41xx_enable_csiint()
378 raw_spin_unlock_irqrestore(&desc->lock, flags); in vr41xx_enable_csiint()
392 raw_spin_lock_irqsave(&desc->lock, flags); in vr41xx_disable_csiint()
394 raw_spin_unlock_irqrestore(&desc->lock, flags); in vr41xx_disable_csiint()
408 raw_spin_lock_irqsave(&desc->lock, flags); in vr41xx_enable_bcuint()
410 raw_spin_unlock_irqrestore(&desc->lock, flags); in vr41xx_enable_bcuint()
424 raw_spin_lock_irqsave(&desc->lock, flags); in vr41xx_disable_bcuint()
426 raw_spin_unlock_irqrestore(&desc->lock, flags); in vr41xx_disable_bcuint()
434 icu1_clear(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(d->irq)); in disable_sysint1_irq()
439 icu1_set(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(d->irq)); in enable_sysint1_irq()
450 icu2_clear(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(d->irq)); in disable_sysint2_irq()
455 icu2_set(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(d->irq)); in enable_sysint2_irq()
472 raw_spin_lock_irq(&desc->lock); in set_sysint1_assign()
511 raw_spin_unlock_irq(&desc->lock); in set_sysint1_assign()
512 return -EINVAL; in set_sysint1_assign()
519 raw_spin_unlock_irq(&desc->lock); in set_sysint1_assign()
532 raw_spin_lock_irq(&desc->lock); in set_sysint2_assign()
579 raw_spin_unlock_irq(&desc->lock); in set_sysint2_assign()
580 return -EINVAL; in set_sysint2_assign()
587 raw_spin_unlock_irq(&desc->lock); in set_sysint2_assign()
594 int retval = -EINVAL; in vr41xx_set_intassign()
597 return -EINVAL; in vr41xx_set_intassign()
600 return -EINVAL; in vr41xx_set_intassign()
645 return -1; in icu_get_irq()
667 return -ENODEV; in vr41xx_icu_init()
671 return -EBUSY; in vr41xx_icu_init()
675 return -EBUSY; in vr41xx_icu_init()
682 return -ENOMEM; in vr41xx_icu_init()
690 return -ENOMEM; in vr41xx_icu_init()