1 // SPDX-License-Identifier: GPL-2.0-or-later
4  * Copyright (C) 2003, 04, 11 Ralf Baechle (ralf@linux-mips.org)
6  *   written by Ralf Baechle (ralf@linux-mips.org)
18 #include <asm/cpu-info.h>
35  * addresses to be allocated in the 0x000-0x0ff region
39  * the low 10 bits of the IO address. The 0x00-0xff region
41  * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
42  * but we want to try to avoid allocating at 0x2900-0x2bff
43  * which might have be mirrored at 0x0100-0x03ff..
50 	struct pci_controller *hose = dev->sysdata;  in pcibios_align_resource()
51 	resource_size_t start = res->start;  in pcibios_align_resource()
53 	if (res->flags & IORESOURCE_IO) {  in pcibios_align_resource()
55 		if (start < PCIBIOS_MIN_IO + hose->io_resource->start)  in pcibios_align_resource()
56 			start = PCIBIOS_MIN_IO + hose->io_resource->start;  in pcibios_align_resource()
59 		 * Put everything into 0x00-0xff region modulo 0x400  in pcibios_align_resource()
63 	} else if (res->flags & IORESOURCE_MEM) {  in pcibios_align_resource()
65 		if (start < PCIBIOS_MIN_MEM + hose->mem_resource->start)  in pcibios_align_resource()
66 			start = PCIBIOS_MIN_MEM + hose->mem_resource->start;  in pcibios_align_resource()
77 	struct pci_bus *bus;  in pcibios_scanbus()  local
85 	if (hose->get_busno && pci_has_flag(PCI_PROBE_ONLY))  in pcibios_scanbus()
86 		next_busno = (*hose->get_busno)();  in pcibios_scanbus()
89 				hose->mem_resource, hose->mem_offset);  in pcibios_scanbus()
91 				hose->io_resource, hose->io_offset);  in pcibios_scanbus()
92 	pci_add_resource(&resources, hose->busn_resource);  in pcibios_scanbus()
93 	list_splice_init(&resources, &bridge->windows);  in pcibios_scanbus()
94 	bridge->dev.parent = NULL;  in pcibios_scanbus()
95 	bridge->sysdata = hose;  in pcibios_scanbus()
96 	bridge->busnr = next_busno;  in pcibios_scanbus()
97 	bridge->ops = hose->pci_ops;  in pcibios_scanbus()
98 	bridge->swizzle_irq = pci_common_swizzle;  in pcibios_scanbus()
99 	bridge->map_irq = pcibios_map_irq;  in pcibios_scanbus()
106 	hose->bus = bus = bridge->bus;  in pcibios_scanbus()
108 	need_domain_info = need_domain_info || pci_domain_nr(bus);  in pcibios_scanbus()
111 	next_busno = bus->busn_res.end + 1;  in pcibios_scanbus()
112 	/* Don't allow 8-bit bus number overflow inside the hose -  in pcibios_scanbus()
125 		pci_bus_claim_resources(bus);  in pcibios_scanbus()
129 		pci_bus_size_bridges(bus);  in pcibios_scanbus()
130 		pci_bus_assign_resources(bus);  in pcibios_scanbus()
131 		list_for_each_entry(child, &bus->children, node)  in pcibios_scanbus()
134 	pci_bus_add_devices(bus);  in pcibios_scanbus()
140 	struct of_pci_range range;  in pci_load_of_ranges()  local
144 	hose->of_node = node;  in pci_load_of_ranges()
149 	for_each_of_pci_range(&parser, &range) {  in pci_load_of_ranges()
152 		switch (range.flags & IORESOURCE_TYPE_BITS) {  in pci_load_of_ranges()
155 				range.cpu_addr,  in pci_load_of_ranges()
156 				range.cpu_addr + range.size - 1);  in pci_load_of_ranges()
157 			hose->io_map_base =  in pci_load_of_ranges()
158 				(unsigned long)ioremap(range.cpu_addr,  in pci_load_of_ranges()
159 						       range.size);  in pci_load_of_ranges()
160 			res = hose->io_resource;  in pci_load_of_ranges()
164 				range.cpu_addr,  in pci_load_of_ranges()
165 				range.cpu_addr + range.size - 1);  in pci_load_of_ranges()
166 			res = hose->mem_resource;  in pci_load_of_ranges()
170 			of_pci_range_to_resource(&range, node, res);  in pci_load_of_ranges()
174 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)  in pcibios_get_phb_of_node()  argument
176 	struct pci_controller *hose = bus->sysdata;  in pcibios_get_phb_of_node()
178 	return of_node_get(hose->of_node);  in pcibios_get_phb_of_node()
188 	parent = hose->mem_resource->parent;  in register_pci_controller()
192 	if (request_resource(parent, hose->mem_resource) < 0)  in register_pci_controller()
195 	parent = hose->io_resource->parent;  in register_pci_controller()
199 	if (request_resource(parent, hose->io_resource) < 0) {  in register_pci_controller()
200 		release_resource(hose->mem_resource);  in register_pci_controller()
204 	INIT_LIST_HEAD(&hose->list);  in register_pci_controller()
205 	list_add_tail(&hose->list, &controllers);  in register_pci_controller()
208 	 * Do not panic here but later - this might happen before console init.  in register_pci_controller()
210 	if (!hose->io_map_base) {  in register_pci_controller()
216 	 * Scan the bus if it is register after the PCI subsystem  in register_pci_controller()
229 	       "Skipping PCI bus scan due to resource conflict\n");  in register_pci_controller()
260 		r = &dev->resource[idx];  in pcibios_enable_resources()
261 		if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))  in pcibios_enable_resources()
264 				(!(r->flags & IORESOURCE_ROM_ENABLE)))  in pcibios_enable_resources()
266 		if (!r->start && r->end) {  in pcibios_enable_resources()
269 			return -EINVAL;  in pcibios_enable_resources()
271 		if (r->flags & IORESOURCE_IO)  in pcibios_enable_resources()
273 		if (r->flags & IORESOURCE_MEM)  in pcibios_enable_resources()
277 		pci_info(dev, "enabling device (%04x -> %04x)\n", old_cmd, cmd);  in pcibios_enable_resources()
293 void pcibios_fixup_bus(struct pci_bus *bus)  in pcibios_fixup_bus()  argument
295 	struct pci_dev *dev = bus->self;  in pcibios_fixup_bus()
298 	    (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {  in pcibios_fixup_bus()
299 		pci_read_bridge_bases(bus);  in pcibios_fixup_bus()