Lines Matching +full:msi +full:- +full:x

6  * Copyright (C) 2005-2009, 2010 Cavium Networks
10 #include <linux/msi.h>
15 #include <asm/octeon/cvmx-npi-defs.h>
16 #include <asm/octeon/cvmx-pci-defs.h>
17 #include <asm/octeon/cvmx-npei-defs.h>
18 #include <asm/octeon/cvmx-sli-defs.h>
19 #include <asm/octeon/cvmx-pexp-defs.h>
20 #include <asm/octeon/pci-octeon.h>
23 * Each bit in msi_free_irq_bitmask represents a MSI interrupt that is
31 * is used so we can disable all of the MSI interrupts when a device
43 * Number of MSI IRQs used. This variable is set up in
49 * Called when a driver request MSI interrupts instead of the
50 * legacy INT A-D. This routine will allocate multiple interrupts
51 * for MSI devices that support them. A device can override this by
52 * programming the MSI control bits [6:4] before calling
55 * @dev: Device requesting MSI interrupts
56 * @desc: MSI descriptor
72 * Read the MSI config to figure out how many IRQs this device in arch_setup_msi_irq()
76 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); in arch_setup_msi_irq()
112 search_mask = (1 << irq_step) - 1; in arch_setup_msi_irq()
116 * bits. This represents an MSI interrupt number that isn't in in arch_setup_msi_irq()
140 panic("arch_setup_msi_irq: Unable to find a free MSI interrupt"); in arch_setup_msi_irq()
143 /* MSI interrupts start at logical IRQ OCTEON_IRQ_MSI_BIT0 */ in arch_setup_msi_irq()
173 msg.data = irq - OCTEON_IRQ_MSI_BIT0; in arch_setup_msi_irq()
178 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); in arch_setup_msi_irq()
191 * MSI-X is not supported. in arch_setup_msi_irqs()
194 return -EINVAL; in arch_setup_msi_irqs()
197 * If an architecture wants to support multiple MSI, it needs to in arch_setup_msi_irqs()
208 return -ENOSPC; in arch_setup_msi_irqs()
215 * Called when a device no longer needs its MSI interrupts. All
216 * MSI interrupts for the device are freed.
230 "MSI interrupt (%d)", irq); in arch_teardown_msi_irq()
232 irq -= OCTEON_IRQ_MSI_BIT0; in arch_teardown_msi_irq()
248 bitmask = (1 << number_irqs) - 1; in arch_teardown_msi_irq()
252 panic("arch_teardown_msi_irq: Attempted to teardown MSI " in arch_teardown_msi_irq()
271 int msi_number = data->irq - OCTEON_IRQ_MSI_BIT0; in octeon_irq_msi_enable_pcie()
287 int msi_number = data->irq - OCTEON_IRQ_MSI_BIT0; in octeon_irq_msi_disable_pcie()
300 .name = "MSI",
308 * Octeon PCI doesn't have the ability to mask/unmask MSI in octeon_irq_msi_enable_pci()
310 * in groups of 16, we simple assume MSI devices are well in octeon_irq_msi_enable_pci()
311 * behaved. MSI interrupts are always enable and the ACK is in octeon_irq_msi_enable_pci()
322 .name = "MSI",
328 * Called by the interrupt handling code when an MSI interrupt
338 bit--; in __octeon_msi_do_interrupt()
349 #define OCTEON_MSI_INT_HANDLER_X(x) \ argument
350 static irqreturn_t octeon_msi_interrupt##x(int cpl, void *dev_id) \
352 u64 msi_bits = cvmx_read_csr(msi_rcv_reg[(x)]); \
353 return __octeon_msi_do_interrupt((x), msi_bits); \
357 * Create octeon_msi_interrupt{0-3} function body
365 * Initializes the MSI interrupt handling code
370 struct irq_chip *msi; in octeon_msi_initialize() local
383 msi = &octeon_irq_chip_msi_pcie; in octeon_msi_initialize()
394 msi = &octeon_irq_chip_msi_pci; in octeon_msi_initialize()
398 irq_set_chip_and_handler(irq, msi, handle_simple_irq); in octeon_msi_initialize()
402 0, "MSI[0:63]", octeon_msi_interrupt0)) in octeon_msi_initialize()
406 0, "MSI[64:127]", octeon_msi_interrupt1)) in octeon_msi_initialize()
410 0, "MSI[127:191]", octeon_msi_interrupt2)) in octeon_msi_initialize()
414 0, "MSI[192:255]", octeon_msi_interrupt3)) in octeon_msi_initialize()
420 0, "MSI[0:15]", octeon_msi_interrupt0)) in octeon_msi_initialize()
424 0, "MSI[16:31]", octeon_msi_interrupt0)) in octeon_msi_initialize()
428 0, "MSI[32:47]", octeon_msi_interrupt0)) in octeon_msi_initialize()
432 0, "MSI[48:63]", octeon_msi_interrupt0)) in octeon_msi_initialize()