1 // SPDX-License-Identifier: GPL-2.0-or-later
17 #include <asm/mips-cps.h>
20 #include <asm/pm-cps.h>
22 #include <asm/smp-cps.h>
73 			for (v = 0; v < min_t(int, core_vpes, NR_CPUS - nvpes); v++) {  in cps_smp_setup()
97 	/* Core 0 is powered up (we're running on it) */  in cps_smp_setup()
112 	/* If we have an FPU, enroll ourselves in the FPU-full mask */  in cps_smp_setup()
126 	/* Detect whether the CCA is unsuited to multi-core SMP */  in cps_prepare_cpus()
131 		/* The CCA is coherent, multi-core is fine */  in cps_prepare_cpus()
136 		/* CCA is not coherent, multi-core is not usable */  in cps_prepare_cpus()
140 	/* Warn the user if the CCA prevents multi-core */  in cps_prepare_cpus()
167 		     (void *)entry_code - (void *)&mips_cps_core_entry);  in cps_prepare_cpus()
264 				timeout--;  in boot_core()
282 	/* The core is now powered up */  in boot_core()
299 	struct vpe_boot_config *vpe_cfg = &core_cfg->vpe_config[vpe_id];  in cps_boot_secondary()
306 		return -ENOSYS;  in cps_boot_secondary()
308 	vpe_cfg->pc = (unsigned long)&smp_bootstrap;  in cps_boot_secondary()
309 	vpe_cfg->sp = __KSTK_TOS(idle);  in cps_boot_secondary()
310 	vpe_cfg->gp = (unsigned long)task_thread_info(idle);  in cps_boot_secondary()
312 	atomic_or(1 << cpu_vpe_id(&cpu_data[cpu]), &core_cfg->vpe_mask);  in cps_boot_secondary()
317 		/* Boot a VPE on a powered down core */  in cps_boot_secondary()
330 		/* Boot a VPE on another powered up core */  in cps_boot_secondary()
352 	/* Boot a VPE on this core */  in cps_boot_secondary()
361 	/* Disable MT - we only want to run 1 TC per VPE */  in cps_init_secondary()
389 	/* If we have an FPU, enroll ourselves in the FPU-full mask */  in cps_smp_finish()
454 		return -EBUSY;  in cps_cpu_disable()
457 		return -EINVAL;  in cps_cpu_disable()
460 	atomic_sub(1 << cpu_vpe_id(&current_cpu_data), &core_cfg->vpe_mask);  in cps_cpu_disable()
539 	 *   - Onlining the CPU again.  in cps_cpu_die()
540 	 *   - Powering down the core if another VPE within it is offlined.  in cps_cpu_die()
541 	 *   - A sibling VPE entering a non-coherent state.  in cps_cpu_die()
543 	 * In the non-MT halt case (ie. infinite loop) the CPU is doing nothing  in cps_cpu_die()
548 		 * Wait for the core to enter a powered down or clock gated  in cps_cpu_die()
568 			 * The core ought to have powered down, but didn't &  in cps_cpu_die()
571 			 * 1 & it powered back up as soon as we powered it  in cps_cpu_die()
579 				 "CPU%u hasn't powered down, seq. state %u\n",  in cps_cpu_die()
584 		/* Indicate the core is powered off */  in cps_cpu_die()
634 		return -ENODEV;  in register_cps_smp_ops()
637 	/* check we have a GIC - we need one for IPIs */  in register_cps_smp_ops()
640 		return -ENODEV;  in register_cps_smp_ops()