Lines Matching +full:8 +full:- +full:cpu
20 #include <linux/cpu.h>
39 #include <asm/cpu-features.h>
52 static void bmips_set_reset_vec(int cpu, u32 val);
56 /* initial $sp, $gp - used by arch/mips/kernel/bmips_vec.S */
60 static void bmips43xx_send_ipi_single(int cpu, unsigned int action);
61 static void bmips5000_send_ipi_single(int cpu, unsigned int action);
69 #define CPUNUM(cpu, shift) (((cpu) + bmips_cpu_offset) << (shift)) argument
70 #define ACTION_CLR_IPI(cpu, ipi) (0x2000 | CPUNUM(cpu, 9) | ((ipi) << 8)) argument
71 #define ACTION_SET_IPI(cpu, ipi) (0x3000 | CPUNUM(cpu, 9) | ((ipi) << 8)) argument
72 #define ACTION_BOOT_THREAD(cpu) (0x08 | CPUNUM(cpu, 0)) argument
76 int i, cpu = 1, boot_cpu = 0; in bmips_smp_setup() local
142 __cpu_number_map[i] = cpu; in bmips_smp_setup()
143 __cpu_logical_map[cpu] = i; in bmips_smp_setup()
144 cpu++; in bmips_smp_setup()
152 * IPI IRQ setup - runs on CPU0
179 * Tell the hardware to boot CPUx - runs on CPU0
181 static int bmips_boot_secondary(int cpu, struct task_struct *idle) in bmips_boot_secondary() argument
188 * Initial boot sequence for secondary CPU: in bmips_boot_secondary()
189 * bmips_reset_nmi_vec @ a000_0000 -> in bmips_boot_secondary()
190 * bmips_smp_entry -> in bmips_boot_secondary()
191 * plat_wired_tlb_setup (cached function call; optional) -> in bmips_boot_secondary()
195 * play_dead WAIT loop -> in bmips_boot_secondary()
196 * bmips_smp_int_vec @ BMIPS_WARM_RESTART_VEC -> in bmips_boot_secondary()
197 * eret to play_dead -> in bmips_boot_secondary()
198 * bmips_secondary_reentry -> in bmips_boot_secondary()
202 pr_info("SMP: Booting CPU%d...\n", cpu); in bmips_boot_secondary()
204 if (cpumask_test_cpu(cpu, &bmips_booted_mask)) { in bmips_boot_secondary()
205 /* kseg1 might not exist if this CPU enabled XKS01 */ in bmips_boot_secondary()
206 bmips_set_reset_vec(cpu, RESET_FROM_KSEG0); in bmips_boot_secondary()
211 bmips43xx_send_ipi_single(cpu, 0); in bmips_boot_secondary()
214 bmips5000_send_ipi_single(cpu, 0); in bmips_boot_secondary()
218 bmips_set_reset_vec(cpu, RESET_FROM_KSEG1); in bmips_boot_secondary()
224 if (cpu_logical_map(cpu) == 1) in bmips_boot_secondary()
228 write_c0_brcm_action(ACTION_BOOT_THREAD(cpu)); in bmips_boot_secondary()
231 cpumask_set_cpu(cpu, &bmips_booted_mask); in bmips_boot_secondary()
238 * Early setup - runs on secondary CPU after cache probe
257 * Late setup - runs on secondary CPU before entering the idle loop
261 pr_info("SMP: CPU%d is running\n", smp_processor_id()); in bmips_smp_finish()
274 * Each CPU has two inbound SW IRQs which are independent of all other CPUs.
279 static void bmips5000_send_ipi_single(int cpu, unsigned int action) in bmips5000_send_ipi_single() argument
281 write_c0_brcm_action(ACTION_SET_IPI(cpu, action == SMP_CALL_FUNCTION)); in bmips5000_send_ipi_single()
286 int action = irq - IPI0_IRQ; in bmips5000_ipi_interrupt()
310 * We use one inbound SW IRQ for each CPU.
320 static void bmips43xx_send_ipi_single(int cpu, unsigned int action) in bmips43xx_send_ipi_single() argument
325 set_c0_cause(cpu ? C_SW1 : C_SW0); in bmips43xx_send_ipi_single()
326 per_cpu(ipi_action_mask, cpu) |= action; in bmips43xx_send_ipi_single()
334 int action, cpu = irq - IPI0_IRQ; in bmips43xx_ipi_interrupt() local
338 per_cpu(ipi_action_mask, cpu) = 0; in bmips43xx_ipi_interrupt()
339 clear_c0_cause(cpu ? C_SW1 : C_SW0); in bmips43xx_ipi_interrupt()
363 unsigned int cpu = smp_processor_id(); in bmips_cpu_disable() local
365 if (cpu == 0) in bmips_cpu_disable()
366 return -EBUSY; in bmips_cpu_disable()
368 pr_info("SMP: CPU%d is offline\n", cpu); in bmips_cpu_disable()
370 set_cpu_online(cpu, false); in bmips_cpu_disable()
381 static void bmips_cpu_die(unsigned int cpu) in bmips_cpu_die() argument
459 memcpy((void *)dst, start, end - start); in bmips_wr_vec()
460 dma_cache_wback(dst, end - start); in bmips_wr_vec()
461 local_flush_icache_range(dst, dst + (end - start)); in bmips_wr_vec()
474 int cpu; member
481 int shift = info->cpu & 0x01 ? 16 : 0; in bmips_set_reset_vec_remote()
482 u32 mask = ~(0xffff << shift), val = info->val >> 16; in bmips_set_reset_vec_remote()
489 if (info->cpu & 0x02) { in bmips_set_reset_vec_remote()
501 static void bmips_set_reset_vec(int cpu, u32 val) in bmips_set_reset_vec() argument
507 info.cpu = cpu; in bmips_set_reset_vec()
513 if (cpu == 0) in bmips_set_reset_vec()
540 * - CPU1 will run this from uncached space in bmips_ebase_setup()
541 * - None of the cacheflush functions are set up yet in bmips_ebase_setup()
543 set_uncached_handler(BMIPS_WARM_RESTART_VEC - CKSEG0, in bmips_ebase_setup()
576 * Called when starting/restarting a secondary CPU. in plat_wired_tlb_setup()
640 " li $8, 0x5a455048\n" in bmips_cpu_setup()
642 " .word 0x4008b008\n" /* mfc0 t0, $22, 8 */ in bmips_cpu_setup()
644 " or $8, $8, $9\n" in bmips_cpu_setup()
645 " .word 0x4088b008\n" /* mtc0 t0, $22, 8 */ in bmips_cpu_setup()
647 " li $8, 0x0\n" in bmips_cpu_setup()
650 : : : "$8", "$9"); in bmips_cpu_setup()
657 " li $8, 0x5a455048\n" in bmips_cpu_setup()
658 " .word 0x4088b00f\n" /* mtc0 $8, $22, 15 */ in bmips_cpu_setup()
660 " .word 0x4008b008\n" /* mfc0 $8, $22, 8 */ in bmips_cpu_setup()
662 " or $8, $9\n" in bmips_cpu_setup()
663 " .word 0x4088b008\n" /* mtc0 $8, $22, 8 */ in bmips_cpu_setup()
664 : : : "$8", "$9"); in bmips_cpu_setup()