mips/kernel/cps-vec.S

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
9 #include <asm/asm-offsets.h>
49 	 * Set dest to non-zero if the core supports the MT ASE, else zero. If
64 	 * Set dest to non-zero if the core supports MIPSr6 multithreading
65 	 * (ie. VPs), else zero. If MIPSr6 multithreading is not supported then
94 .section .text.cps-vec
162 	/* Skip core-level init if we started up coherent */
166 	/* Perform any further required core-level initialisation */
271 	/* Set exclusive TC, non-active, master */
277 	/* Set TC non-active, non-allocatable */
278 	mttc0	zero, CP0_TCSTATUS
302  * mips_cps_get_bootcfg() - retrieve boot configuration pointers
323 	 * Assume non-contiguous numbering. Perhaps some day we'll need
344 	addiu	t1, t1, -1
454 	 * CONFIG3 must exist to be running MT startup - just read it.
468 	mttc0	zero, CP0_CAUSE
469 	mttc0	zero, CP0_STATUS
479 	mttc0	zero, CP0_TCHALT
531 	mtc0	zero, CP0_TAGLO, 0
532 	mtc0	zero, CP0_TAGHI, 0
533 	mtc0	zero, CP0_TAGLO, 2
534 	mtc0	zero, CP0_TAGHI, 2
540 	/* Detect I-cache line size */
546 	/* Detect I-cache size */
553 1:	/* At this point t1 == I-cache sets per way */
567 	/* Detect D-cache line size */
573 	/* Detect D-cache size */
580 1:	/* At this point t1 == D-cache sets per way */