mips/kernel/bmips_5xxx_init.S

7  * Copyright (C) 2011-2012 by Broadcom Corporation
28 #define cacheop(kva, size, linesize, op) 	\  argument
30 	addu		t1, kva, size	;	\
34 	addiu		t1, t1, -1	;	\
36 9:	cache		op, 0(t0)	;	\
80 /* ZSC L2 Cache Register Access Register Definitions */
111  * Returns:	v0 = i cache size, v1 = I cache line size
112  * Description: compute the I-cache size and I-cache line size
129 	 * the instruction cache:
131 	 * vi) 0x5 - 0x7: Reserved.
143 	 * Determine line size
145 	 * This field contains the line size of the instruction cache:
146 	 * i) 0x0: No I-cache present, i) 0x3: 16 bytes, ii) 0x4: 32 bytes, iii)
158 	/* line size = 2 ^ (IL+1) */
164 	/* v0 now have sets per way, multiply it by line size now
165 	 * that will give the set size
173 	 * This field contains the set associativity of the instruction cache.
174 	 * i) 0x0: Direct mapped, ii) 0x1: 2-way, iii) 0x2: 3-way, iv) 0x3:
175 	 * 4-way, v) 0x4 - 0x7: Reserved.
184 	/* v0 has the set size, multiply it by
185 	 * set associativiy, to get the cache size
206  * Returns:	v0 = d cache size, v1 = d cache line size
207  * Description: compute the D-cache size and D-cache line size.
222 	 * the instruction cache:
224 	 * vi) 0x5 - 0x7: Reserved.
236 	 * Determine line size
238 	 * This field contains the line size of the instruction cache:
239 	 * i) 0x0: No I-cache present, i) 0x3: 16 bytes, ii) 0x4: 32 bytes, iii)
250 	/* line size = 2 ^ (IL+1) */
256 	/* v0 now have sets per way, multiply it by line size now
257 	 * that will give the set size
264 	 * This field contains the set associativity of the instruction cache.
265 	 * i) 0x0: Direct mapped, ii) 0x1: 2-way, iii) 0x2: 3-way, iv) 0x3:
266 	 * 4-way, v) 0x4 - 0x7: Reserved.
275 	/* v0 has the set size, multiply it by
276 	 * set associativiy, to get the cache size
300  * Description: Enable I and D caches, initialize I and D-caches, also set
301  *		hardware delay for d-cache (TP0).
323  * Description: Enable I and D caches, and initialize I and D-caches
336 	/* initialize I and D cache Data and Tag registers.  */
345 	 * then the cache operations to clear the cache will be ignored
351 	jal	size_i_cache	/* v0 = i-cache size, v1 = i-cache line size */
363 	 * set K0 cache mode
372 	 * Initialize instruction cache.
379 	 * Now we can run from I-$, kseg 0
389 	 * Initialize data cache.
392 	jal	size_d_cache	/* v0 = d-cache size, v1 = d-cache line size */
419 	/* enable Bus error for I-fetch */
591 	cache	0x7, 0x0(t2)
607 	cache	0xb, 0x0(t2)
715  * Description: Enable I and D caches, and initialize I and D-caches