2  * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
38 /* PIC Specific registers */
41 /* PIC control register defines */
52 /* PIC Status register defines */
59 /* PIC IPI control register offsets */
62 #define PIC_IPICTRL_IDB		16 /* interrupt destination base */
65 /* PIC IRT register offsets */
71 #define PIC_IRT_DB		16 /* Destination base */
223 /* We use PIC on node 0 as a timer */
228 nlm_9xx_pic_write_irt(uint64_t base, int irt_num, int en, int nmi,  in nlm_9xx_pic_write_irt()  argument
229 	int sch, int vec, int dt, int db, int cpu)  in nlm_9xx_pic_write_irt()  argument
234 			((0 /*mc*/) << 20) | ((vec & 0x3f) << 24) |  in nlm_9xx_pic_write_irt()
238 	nlm_write_pic_reg(base, PIC_9XX_IRT(irt_num), val);  in nlm_9xx_pic_write_irt()
242 nlm_pic_write_irt(uint64_t base, int irt_num, int en, int nmi,  in nlm_pic_write_irt()  argument
243 	int sch, int vec, int dt, int db, int dte)  in nlm_pic_write_irt()  argument
248 			((sch & 0x1) << 28) | ((vec & 0x3f) << 20) |  in nlm_pic_write_irt()
252 	nlm_write_pic_reg(base, PIC_IRT(irt_num), val);  in nlm_pic_write_irt()
256 nlm_pic_write_irt_direct(uint64_t base, int irt_num, int en, int nmi,  in nlm_pic_write_irt_direct()  argument
257 	int sch, int vec, int cpu)  in nlm_pic_write_irt_direct()  argument
260 		nlm_9xx_pic_write_irt(base, irt_num, en, nmi, sch, vec,  in nlm_pic_write_irt_direct()
263 		nlm_pic_write_irt(base, irt_num, en, nmi, sch, vec, 1,  in nlm_pic_write_irt_direct()
269 nlm_pic_read_timer(uint64_t base, int timer)  in nlm_pic_read_timer()  argument
271 	return nlm_read_pic_reg(base, PIC_TIMER_COUNT(timer));  in nlm_pic_read_timer()
275 nlm_pic_read_timer32(uint64_t base, int timer)  in nlm_pic_read_timer32()  argument
277 	return (uint32_t)nlm_read_pic_reg(base, PIC_TIMER_COUNT(timer));  in nlm_pic_read_timer32()
281 nlm_pic_write_timer(uint64_t base, int timer, uint64_t value)  in nlm_pic_write_timer()  argument
283 	nlm_write_pic_reg(base, PIC_TIMER_COUNT(timer), value);  in nlm_pic_write_timer()
287 nlm_pic_set_timer(uint64_t base, int timer, uint64_t value, int irq, int cpu)  in nlm_pic_set_timer()  argument
289 	uint64_t pic_ctrl = nlm_read_pic_reg(base, PIC_CTRL);  in nlm_pic_set_timer()
293 	nlm_write_pic_reg(base, PIC_TIMER_MAXVAL(timer), value);  in nlm_pic_set_timer()
294 	nlm_pic_write_irt_direct(base, PIC_IRT_TIMER_INDEX(timer),  in nlm_pic_set_timer()
299 	nlm_write_pic_reg(base, PIC_CTRL, pic_ctrl);  in nlm_pic_set_timer()
303 nlm_pic_enable_irt(uint64_t base, int irt)  in nlm_pic_enable_irt()  argument
308 		reg = nlm_read_pic_reg(base, PIC_9XX_IRT(irt));  in nlm_pic_enable_irt()
309 		nlm_write_pic_reg(base, PIC_9XX_IRT(irt), reg | (1 << 22));  in nlm_pic_enable_irt()
311 		reg = nlm_read_pic_reg(base, PIC_IRT(irt));  in nlm_pic_enable_irt()
312 		nlm_write_pic_reg(base, PIC_IRT(irt), reg | (1u << 31));  in nlm_pic_enable_irt()
317 nlm_pic_disable_irt(uint64_t base, int irt)  in nlm_pic_disable_irt()  argument
322 		reg = nlm_read_pic_reg(base, PIC_9XX_IRT(irt));  in nlm_pic_disable_irt()
324 		nlm_write_pic_reg(base, PIC_9XX_IRT(irt), reg);  in nlm_pic_disable_irt()
326 		reg = nlm_read_pic_reg(base, PIC_IRT(irt));  in nlm_pic_disable_irt()
328 		nlm_write_pic_reg(base, PIC_IRT(irt), reg);  in nlm_pic_disable_irt()
333 nlm_pic_send_ipi(uint64_t base, int hwt, int irq, int nmi)  in nlm_pic_send_ipi()  argument
344 	nlm_write_pic_reg(base, PIC_IPI_CTL, ipi);  in nlm_pic_send_ipi()
348 nlm_pic_ack(uint64_t base, int irt_num)  in nlm_pic_ack()  argument
350 	nlm_write_pic_reg(base, PIC_INT_ACK, irt_num);  in nlm_pic_ack()
354 		nlm_write_pic_reg(base, PIC_STATUS, (1 << irt_num));  in nlm_pic_ack()
358 nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt, int en)  in nlm_pic_init_irt()  argument
360 	nlm_pic_write_irt_direct(base, irt, en, 0, 0, irq, hwt);  in nlm_pic_init_irt()