Lines Matching +full:0 +full:x414
38 #define CPU_BLOCKID_IFU 0
49 #define IFU_BRUB_RESERVE 0x007
51 #define ICU_DEFEATURE 0x100
53 #define LSU_DEFEATURE 0x304
54 #define LSU_DEBUG_ADDR 0x305
55 #define LSU_DEBUG_DATA0 0x306
56 #define LSU_CERRLOG_REGID 0x309
57 #define SCHED_DEFEATURE 0x700
60 #define MAP_THREADMODE 0x00
61 #define MAP_EXT_EBASE_ENABLE 0x04
62 #define MAP_CCDI_CONFIG 0x08
63 #define MAP_THRD0_CCDI_STATUS 0x0c
64 #define MAP_THRD1_CCDI_STATUS 0x10
65 #define MAP_THRD2_CCDI_STATUS 0x14
66 #define MAP_THRD3_CCDI_STATUS 0x18
67 #define MAP_THRD0_DEBUG_MODE 0x1c
68 #define MAP_THRD1_DEBUG_MODE 0x20
69 #define MAP_THRD2_DEBUG_MODE 0x24
70 #define MAP_THRD3_DEBUG_MODE 0x28
71 #define MAP_MISC_STATE 0x60
72 #define MAP_DEBUG_READ_CTL 0x64
73 #define MAP_DEBUG_READ_REG0 0x68
74 #define MAP_DEBUG_READ_REG1 0x6c
76 #define MMU_SETUP 0x400
77 #define MMU_LFSRSEED 0x401
78 #define MMU_HPW_NUM_PAGE_LVL 0x410
79 #define MMU_PGWKR_PGDBASE 0x411
80 #define MMU_PGWKR_PGDSHFT 0x412
81 #define MMU_PGWKR_PGDMASK 0x413
82 #define MMU_PGWKR_PUDSHFT 0x414
83 #define MMU_PGWKR_PUDMASK 0x415
84 #define MMU_PGWKR_PMDSHFT 0x416
85 #define MMU_PGWKR_PMDMASK 0x417
86 #define MMU_PGWKR_PTESHFT 0x418
87 #define MMU_PGWKR_PTEMASK 0x419