include/asm/mipsregs.h

19 #include <asm/isa-rev.h>
45  * Coprocessor 0 register names
101  * R4640/R4650 cp0 register names.  These registers are listed
115  * Coprocessor 0 Set 1 register names
122  * Coprocessor 0 Set 2 register names
127  * Coprocessor 0 Set 3 register names
152 #define MIPS_ENTRYLO_XI		(_ULCAST_(1) << (BITS_PER_LONG - 2))
153 #define MIPS_ENTRYLO_RI		(_ULCAST_(1) << (BITS_PER_LONG - 1))
392 /* in-kernel enabled CUs */
470 #define EXCCODE_TLBRI		19	/* TLB Read-Inhibit exception */
471 #define EXCCODE_TLBXI		20	/* TLB Execution-Inhibit exception */
485 #define LOONGSON_EXCCODE_GSEXC	16	/* Loongson-specific exception */
667 /* bits 10:8 in FTLB-only configurations */
669 /* bits 12:8 in VTLB-FTLB only configurations */
718 /* Config6 feature bits for Loongson-3 */
720 /* Loongson-3 internal timer bit */
722 /* Loongson-3 external timer bit */
724 /* Loongson-3 SFB on/off bit, STFill in manual */
726 /* Loongson-3's LL on exclusive cacheline */
728 /* Loongson-3's SC has a random delay */
730 /* Loongson-3 FTLB on/off bit, VTLBOnly in manual */
826 #define MIPS_EBASE_BASE		(~_ULCAST_((1 << MIPS_EBASE_BASE_SHIFT) - 1))
830 #define MIPS_CMGCRF_BASE	(~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
961 #define MIPS_GCTL0EXT_RPW_BOTH	0  /* Root PW for GPA->RPA and RVA->RPA */
962 #define MIPS_GCTL0EXT_RPW_GPA	2  /* Root PW for GPA->RPA */
963 #define MIPS_GCTL0EXT_RPW_RVA	3  /* Root PW for RVA->RPA */
1066  * Diag1 (GSCause in Loongson-speak) fields
1068 /* Loongson-specific exception code (GSExcCode) */
1089  * Coprocessor 1 (FPU) register names
1212 #define FPU_CSR_RD	0x3	/* towards -Infinity */
1232  * microMIPS instructions can be 16-bit or 32-bit in length. This
1233  * returns a 1 if the instruction is 16-bit and a 0 if 32-bit.
1270  * parse_r var, r - Helper assembler macro for parsing register names.
1297 	"\\var	= -1\n\t"
1316  * The names of the operands can be chosen by the caller, and the encoding of
1376  * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
1378  * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
1508 #define __read_ulong_c0_register(reg, sel)				\  argument
1510 	(unsigned long) __read_32bit_c0_register(reg, sel) :		\
1511 	(unsigned long) __read_64bit_c0_register(reg, sel))
1513 #define __read_const_ulong_c0_register(reg, sel)			\  argument
1515 	(unsigned long) __read_const_32bit_c0_register(reg, sel) :	\
1516 	(unsigned long) __read_const_64bit_c0_register(reg, sel))
1518 #define __write_ulong_c0_register(reg, sel, val)			\  argument
1521 		__write_32bit_c0_register(reg, sel, val);		\
1523 		__write_64bit_c0_register(reg, sel, val);		\
1546  * physical address space running the 32-bit kernel.  That's none atm :-)
2122 #define __read_ulong_gc0_register(reg, sel)				\  argument
2124 	(unsigned long) __read_32bit_gc0_register(reg, sel) :		\
2125 	(unsigned long) __read_64bit_gc0_register(reg, sel))
2127 #define __write_ulong_gc0_register(reg, sel, val)			\  argument
2130 		__write_32bit_gc0_register(reg, sel, val);		\
2132 		__write_64bit_gc0_register(reg, sel, val);		\
2673 #define _dsp_mflo(reg) _dsp_mfxxx((reg << 14) | 0x1000)  argument
2674 #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 14) | 0x0000)  argument
2676 #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x1000))  argument
2677 #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x0000))  argument
2681 #define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)  argument
2682 #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)  argument
2684 #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))  argument
2685 #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))  argument