include/asm/mipsregs.h

19 #include <asm/isa-rev.h>
84 #define CP0_WATCHLO $18
92 #define CP0_PERFORMANCE $25
111 #define CP0_IWATCH $18
152 #define MIPS_ENTRYLO_XI		(_ULCAST_(1) << (BITS_PER_LONG - 2))
153 #define MIPS_ENTRYLO_RI		(_ULCAST_(1) << (BITS_PER_LONG - 1))
248 #define PL_256K		18
392 /* in-kernel enabled CUs */
470 #define EXCCODE_TLBRI		19	/* TLB Read-Inhibit exception */
471 #define EXCCODE_TLBXI		20	/* TLB Execution-Inhibit exception */
476 #define EXCCODE_THREAD		25	/* Thread exceptions (MT) */
485 #define LOONGSON_EXCCODE_GSEXC	16	/* Loongson-specific exception */
512 #define CONF_EW			(_ULCAST_(3) << 18)
559 #define R30XX_CONF_HALT		(_ULCAST_(1) << 25)
568 #define TX49_CONF_HALT		(_ULCAST_(1) << 18)
587 #define MIPS_CONF_KU		(_ULCAST_(3) << 25)
619 #define MIPS_CONF1_TLBS_SHIFT   (25)
649 #define MIPS_CONF3_MMAR		(_ULCAST_(7) << 18)
653 #define MIPS_CONF3_SC		(_ULCAST_(1) << 25)
667 /* bits 10:8 in FTLB-only configurations */
669 /* bits 12:8 in VTLB-FTLB only configurations */
694 #define MIPS_CONF5_CRCP		(_ULCAST_(1) << 18)
718 /* Config6 feature bits for Loongson-3 */
720 /* Loongson-3 internal timer bit */
722 /* Loongson-3 external timer bit */
724 /* Loongson-3 SFB on/off bit, STFill in manual */
726 /* Loongson-3's LL on exclusive cacheline */
728 /* Loongson-3's SC has a random delay */
730 /* Loongson-3 FTLB on/off bit, VTLBOnly in manual */
826 #define MIPS_EBASE_BASE		(~_ULCAST_((1 << MIPS_EBASE_BASE_SHIFT) - 1))
830 #define MIPS_CMGCRF_BASE	(~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
858 #define MIPS_PWFIELD_UDI_SHIFT	18
871 #define MIPS_PWSIZE_UDW_SHIFT	18
906 #define MIPS_GCTL0_GT_SHIFT	25
916 #define MIPS_GCTL0_PT_SHIFT	18
961 #define MIPS_GCTL0EXT_RPW_BOTH	0  /* Root PW for GPA->RPA and RVA->RPA */
962 #define MIPS_GCTL0EXT_RPW_GPA	2  /* Root PW for GPA->RPA */
963 #define MIPS_GCTL0EXT_RPW_RVA	3  /* Root PW for RVA->RPA */
1066  * Diag1 (GSCause in Loongson-speak) fields
1068 /* Loongson-specific exception code (GSExcCode) */
1094 #define CP1_FCCR	$25
1105 #define MIPS_FPIR_PS		(_ULCAST_(1) << 18)
1151 #define FPU_CSR_CONDX_S	25					/* $fcc[7:1] */
1153 #define FPU_CSR_COND1_S	25					/* $fcc1 */
1178 #define FPU_CSR_NAN2008	(_ULCAST_(1) << 18)
1212 #define FPU_CSR_RD	0x3	/* towards -Infinity */
1232  * microMIPS instructions can be 16-bit or 32-bit in length. This
1233  * returns a 1 if the instruction is 16-bit and a 0 if 32-bit.
1270  * parse_r var, r - Helper assembler macro for parsing register names.
1297 	"\\var	= -1\n\t"
1302 	_IFC_REG(16) _IFC_REG(17) _IFC_REG(18) _IFC_REG(19)
1304 	_IFC_REG(24) _IFC_REG(25) _IFC_REG(26) _IFC_REG(27)
1376  * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
1378  * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
1546  * physical address space running the 32-bit kernel.  That's none atm :-)
1783 #define read_c0_watchlo0()	__read_ulong_c0_register($18, 0)
1784 #define read_c0_watchlo1()	__read_ulong_c0_register($18, 1)
1785 #define read_c0_watchlo2()	__read_ulong_c0_register($18, 2)
1786 #define read_c0_watchlo3()	__read_ulong_c0_register($18, 3)
1787 #define read_c0_watchlo4()	__read_ulong_c0_register($18, 4)
1788 #define read_c0_watchlo5()	__read_ulong_c0_register($18, 5)
1789 #define read_c0_watchlo6()	__read_ulong_c0_register($18, 6)
1790 #define read_c0_watchlo7()	__read_ulong_c0_register($18, 7)
1791 #define write_c0_watchlo0(val)	__write_ulong_c0_register($18, 0, val)
1792 #define write_c0_watchlo1(val)	__write_ulong_c0_register($18, 1, val)
1793 #define write_c0_watchlo2(val)	__write_ulong_c0_register($18, 2, val)
1794 #define write_c0_watchlo3(val)	__write_ulong_c0_register($18, 3, val)
1795 #define write_c0_watchlo4(val)	__write_ulong_c0_register($18, 4, val)
1796 #define write_c0_watchlo5(val)	__write_ulong_c0_register($18, 5, val)
1797 #define write_c0_watchlo6(val)	__write_ulong_c0_register($18, 6, val)
1798 #define write_c0_watchlo7(val)	__write_ulong_c0_register($18, 7, val)
1861 #define read_c0_perfctrl0()	__read_32bit_c0_register($25, 0)
1862 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
1863 #define read_c0_perfcntr0()	__read_32bit_c0_register($25, 1)
1864 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
1865 #define read_c0_perfcntr0_64()	__read_64bit_c0_register($25, 1)
1866 #define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
1867 #define read_c0_perfctrl1()	__read_32bit_c0_register($25, 2)
1868 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
1869 #define read_c0_perfcntr1()	__read_32bit_c0_register($25, 3)
1870 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
1871 #define read_c0_perfcntr1_64()	__read_64bit_c0_register($25, 3)
1872 #define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
1873 #define read_c0_perfctrl2()	__read_32bit_c0_register($25, 4)
1874 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
1875 #define read_c0_perfcntr2()	__read_32bit_c0_register($25, 5)
1876 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
1877 #define read_c0_perfcntr2_64()	__read_64bit_c0_register($25, 5)
1878 #define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
1879 #define read_c0_perfctrl3()	__read_32bit_c0_register($25, 6)
1880 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
1881 #define read_c0_perfcntr3()	__read_32bit_c0_register($25, 7)
1882 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
1883 #define read_c0_perfcntr3_64()	__read_64bit_c0_register($25, 7)
1884 #define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
2246 #define read_gc0_watchlo0()		__read_ulong_gc0_register($18, 0)
2247 #define read_gc0_watchlo1()		__read_ulong_gc0_register($18, 1)
2248 #define read_gc0_watchlo2()		__read_ulong_gc0_register($18, 2)
2249 #define read_gc0_watchlo3()		__read_ulong_gc0_register($18, 3)
2250 #define read_gc0_watchlo4()		__read_ulong_gc0_register($18, 4)
2251 #define read_gc0_watchlo5()		__read_ulong_gc0_register($18, 5)
2252 #define read_gc0_watchlo6()		__read_ulong_gc0_register($18, 6)
2253 #define read_gc0_watchlo7()		__read_ulong_gc0_register($18, 7)
2254 #define write_gc0_watchlo0(val)		__write_ulong_gc0_register($18, 0, val)
2255 #define write_gc0_watchlo1(val)		__write_ulong_gc0_register($18, 1, val)
2256 #define write_gc0_watchlo2(val)		__write_ulong_gc0_register($18, 2, val)
2257 #define write_gc0_watchlo3(val)		__write_ulong_gc0_register($18, 3, val)
2258 #define write_gc0_watchlo4(val)		__write_ulong_gc0_register($18, 4, val)
2259 #define write_gc0_watchlo5(val)		__write_ulong_gc0_register($18, 5, val)
2260 #define write_gc0_watchlo6(val)		__write_ulong_gc0_register($18, 6, val)
2261 #define write_gc0_watchlo7(val)		__write_ulong_gc0_register($18, 7, val)
2283 #define read_gc0_perfctrl0()		__read_32bit_gc0_register($25, 0)
2284 #define write_gc0_perfctrl0(val)	__write_32bit_gc0_register($25, 0, val)
2285 #define read_gc0_perfcntr0()		__read_32bit_gc0_register($25, 1)
2286 #define write_gc0_perfcntr0(val)	__write_32bit_gc0_register($25, 1, val)
2287 #define read_gc0_perfcntr0_64()		__read_64bit_gc0_register($25, 1)
2288 #define write_gc0_perfcntr0_64(val)	__write_64bit_gc0_register($25, 1, val)
2289 #define read_gc0_perfctrl1()		__read_32bit_gc0_register($25, 2)
2290 #define write_gc0_perfctrl1(val)	__write_32bit_gc0_register($25, 2, val)
2291 #define read_gc0_perfcntr1()		__read_32bit_gc0_register($25, 3)
2292 #define write_gc0_perfcntr1(val)	__write_32bit_gc0_register($25, 3, val)
2293 #define read_gc0_perfcntr1_64()		__read_64bit_gc0_register($25, 3)
2294 #define write_gc0_perfcntr1_64(val)	__write_64bit_gc0_register($25, 3, val)
2295 #define read_gc0_perfctrl2()		__read_32bit_gc0_register($25, 4)
2296 #define write_gc0_perfctrl2(val)	__write_32bit_gc0_register($25, 4, val)
2297 #define read_gc0_perfcntr2()		__read_32bit_gc0_register($25, 5)
2298 #define write_gc0_perfcntr2(val)	__write_32bit_gc0_register($25, 5, val)
2299 #define read_gc0_perfcntr2_64()		__read_64bit_gc0_register($25, 5)
2300 #define write_gc0_perfcntr2_64(val)	__write_64bit_gc0_register($25, 5, val)
2301 #define read_gc0_perfctrl3()		__read_32bit_gc0_register($25, 6)
2302 #define write_gc0_perfctrl3(val)	__write_32bit_gc0_register($25, 6, val)
2303 #define read_gc0_perfcntr3()		__read_32bit_gc0_register($25, 7)
2304 #define write_gc0_perfcntr3(val)	__write_32bit_gc0_register($25, 7, val)
2305 #define read_gc0_perfcntr3_64()		__read_64bit_gc0_register($25, 7)
2306 #define write_gc0_perfcntr3_64(val)	__write_64bit_gc0_register($25, 7, val)