include/asm/mips-cm.h

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 # error Please include asm/mips-cps.h rather than asm/mips-cm.h
20 /* The base address of the CM L2-only sync region */
24  * __mips_cm_phys_base - retrieve the physical base address of the CM
36  * mips_cm_is64 - determine CM register width
39  * introducing 64 bit GCRs and all prior CM versions having 32 bit GCRs.
40  * However we may run a kernel built for MIPS32 on a system with 64 bit GCRs,
41  * or vice-versa. This variable indicates the width of the memory accesses
45  * It's set to 0 for 32-bit accesses and 1 for 64-bit accesses.
50  * mips_cm_error_report - Report CM cache errors
59  * mips_cm_probe - probe for a Coherence Manager
62  * is successfully detected, else -errno.
69 	return -ENODEV;  in mips_cm_probe()
74  * mips_cm_present - determine whether a Coherence Manager is present
88  * mips_cm_has_l2sync - determine whether an L2-only sync region is present
90  * Returns true if the system implements an L2-only sync region, else false.
110 /* Size of the L2-only sync region */
129 /* GCR_CONFIG - Information about the system */
130 GCR_ACCESSOR_RO(64, 0x000, config)
137 /* GCR_BASE - Base address of the Global Configuration Registers (GCRs) */
138 GCR_ACCESSOR_RW(64, 0x008, base)
146 /* GCR_ACCESS - Controls core/IOCU access to GCRs */
150 /* GCR_REV - Indicates the Coherence Manager revision */
164 /* GCR_ERR_CONTROL - Control error checking logic */
166 #define CM_GCR_ERR_CONTROL_L2_ECC_EN		BIT(1)
167 #define CM_GCR_ERR_CONTROL_L2_ECC_SUPPORT	BIT(0)
169 /* GCR_ERR_MASK - Control which errors are reported as interrupts */
170 GCR_ACCESSOR_RW(64, 0x040, error_mask)
172 /* GCR_ERR_CAUSE - Indicates the type of error that occurred */
173 GCR_ACCESSOR_RW(64, 0x048, error_cause)
178 /* GCR_ERR_ADDR - Indicates the address associated with an error */
179 GCR_ACCESSOR_RW(64, 0x050, error_addr)
181 /* GCR_ERR_MULT - Indicates when multiple errors have occurred */
182 GCR_ACCESSOR_RW(64, 0x058, error_mult)
185 /* GCR_L2_ONLY_SYNC_BASE - Base address of the L2 cache-only sync region */
186 GCR_ACCESSOR_RW(64, 0x070, l2_only_sync_base)
188 #define CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN		BIT(0)
190 /* GCR_GIC_BASE - Base address of the Global Interrupt Controller (GIC) */
191 GCR_ACCESSOR_RW(64, 0x080, gic_base)
193 #define CM_GCR_GIC_BASE_GICEN			BIT(0)
195 /* GCR_CPC_BASE - Base address of the Cluster Power Controller (CPC) */
196 GCR_ACCESSOR_RW(64, 0x088, cpc_base)
198 #define CM_GCR_CPC_BASE_CPCEN			BIT(0)
200 /* GCR_REGn_BASE - Base addresses of CM address regions */
201 GCR_ACCESSOR_RW(64, 0x090, reg0_base)
202 GCR_ACCESSOR_RW(64, 0x0a0, reg1_base)
203 GCR_ACCESSOR_RW(64, 0x0b0, reg2_base)
204 GCR_ACCESSOR_RW(64, 0x0c0, reg3_base)
207 /* GCR_REGn_MASK - Size & destination of CM address regions */
208 GCR_ACCESSOR_RW(64, 0x098, reg0_mask)
209 GCR_ACCESSOR_RW(64, 0x0a8, reg1_mask)
210 GCR_ACCESSOR_RW(64, 0x0b8, reg2_mask)
211 GCR_ACCESSOR_RW(64, 0x0c8, reg3_mask)
214 #define CM_GCR_REGn_MASK_CCAOVREN		BIT(4)
215 #define CM_GCR_REGn_MASK_DROPL2			BIT(2)
222 /* GCR_GIC_STATUS - Indicates presence of a Global Interrupt Controller (GIC) */
224 #define CM_GCR_GIC_STATUS_EX			BIT(0)
226 /* GCR_CPC_STATUS - Indicates presence of a Cluster Power Controller (CPC) */
228 #define CM_GCR_CPC_STATUS_EX			BIT(0)
230 /* GCR_L2_CONFIG - Indicates L2 cache configuration when Config5.L2C=1 */
232 #define CM_GCR_L2_CONFIG_BYPASS			BIT(20)
237 /* GCR_SYS_CONFIG2 - Further information about the system */
241 /* GCR_L2_PFT_CONTROL - Controls hardware L2 prefetching */
244 #define CM_GCR_L2_PFT_CONTROL_PFTEN		BIT(8)
247 /* GCR_L2_PFT_CONTROL_B - Controls hardware L2 prefetching */
249 #define CM_GCR_L2_PFT_CONTROL_B_CEN		BIT(8)
252 /* GCR_L2SM_COP - L2 cache op state machine control */
254 #define CM_GCR_L2SM_COP_PRESENT			BIT(31)
261 #define CM_GCR_L2SM_COP_RUNNING			BIT(5)
274 /* GCR_L2SM_TAG_ADDR_COP - L2 cache op state machine address control */
275 GCR_ACCESSOR_RW(64, 0x628, l2sm_tag_addr_cop)
279 /* GCR_BEV_BASE - Controls the location of the BEV for powered up cores */
280 GCR_ACCESSOR_RW(64, 0x680, bev_base)
282 /* GCR_Cx_RESET_RELEASE - Controls core reset for CM 1.x */
285 /* GCR_Cx_COHERENCE - Controls core coherence */
288 #define CM3_GCR_Cx_COHERENCE_COHEN		BIT(0)
290 /* GCR_Cx_CONFIG - Information about a core's configuration */
295 /* GCR_Cx_OTHER - Configure the core-other/redirect GCR block */
298 #define CM_GCR_Cx_OTHER_CLUSTER_EN		BIT(31)		/* CM >= 3.5 */
299 #define CM_GCR_Cx_OTHER_GIC_EN			BIT(30)		/* CM >= 3.5 */
310 /* GCR_Cx_RESET_BASE - Configure where powered up cores will fetch from */
314 /* GCR_Cx_ID - Identify the current core */
319 /* GCR_Cx_RESET_EXT_BASE - Configure behaviour when cores reset or power up */
321 #define CM_GCR_Cx_RESET_EXT_BASE_EVARESET	BIT(31)
322 #define CM_GCR_Cx_RESET_EXT_BASE_UEB		BIT(30)
325 #define CM_GCR_Cx_RESET_EXT_BASE_PRESENT	BIT(0)
328  * mips_cm_l2sync - perform an L2-only sync operation
330  * If an L2-only sync region is present in the system then this function
331  * performs and L2-only sync and returns zero. Otherwise it returns -ENODEV.
336 		return -ENODEV;  in mips_cm_l2sync()
343  * mips_cm_revision() - return CM revision
357  * mips_cm_max_vp_width() - return the width in bits of VP indices
387  * mips_cm_vp_id() - calculate the hardware VP ID for a CPU
407  * mips_cm_lock_other - lock access to redirect/other region
420  * mips_cm_unlock_other() calls cannot be pre-empted by anything which may
428  * mips_cm_unlock_other - unlock access to redirect/other region
444  * mips_cm_lock_other_cpu - lock access to redirect/other region