Lines Matching +full:reg +full:- +full:names
1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <93750000>;
16 reg = <0>;
22 reg = <1>;
30 cpu_intc: interrupt-controller {
31 #address-cells = <0>;
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
35 #interrupt-cells = <1>;
40 compatible = "fixed-clock";
41 #clock-cells = <0>;
42 clock-frequency = <81000000>;
46 compatible = "fixed-clock";
47 #clock-cells = <0>;
48 clock-frequency = <27000000>;
53 #address-cells = <1>;
54 #size-cells = <1>;
56 compatible = "simple-bus";
59 periph_intc: interrupt-controller@441400 {
60 compatible = "brcm,bcm7038-l1-intc";
61 reg = <0x441400 0x30>, <0x441600 0x30>;
63 interrupt-controller;
64 #interrupt-cells = <1>;
66 interrupt-parent = <&cpu_intc>;
70 sun_l2_intc: interrupt-controller@401800 {
71 compatible = "brcm,l2-intc";
72 reg = <0x401800 0x30>;
73 interrupt-controller;
74 #interrupt-cells = <1>;
75 interrupt-parent = <&periph_intc>;
79 gisb-arb@400000 {
80 compatible = "brcm,bcm7400-gisb-arb";
81 reg = <0x400000 0xdc>;
82 native-endian;
83 interrupt-parent = <&sun_l2_intc>;
85 brcm,gisb-arb-master-mask = <0x3ff>;
86 brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "pci_0",
92 upg_irq0_intc: interrupt-controller@406780 {
93 compatible = "brcm,bcm7120-l2-intc";
94 reg = <0x406780 0x8>;
96 brcm,int-map-mask = <0x44>, <0x1f000000>, <0x100000>;
97 brcm,int-fwd-mask = <0x70000>;
99 interrupt-controller;
100 #interrupt-cells = <1>;
102 interrupt-parent = <&periph_intc>;
104 interrupt-names = "upg_main", "upg_bsc", "upg_spi";
108 compatible = "brcm,bcm7420-sun-top-ctrl", "syscon";
109 reg = <0x404000 0x60c>;
110 native-endian;
114 compatible = "brcm,bcm7038-reboot";
120 reg = <0x406b00 0x20>;
121 reg-io-width = <0x4>;
122 reg-shift = <0x2>;
123 interrupt-parent = <&periph_intc>;
131 reg = <0x406b40 0x20>;
132 reg-io-width = <0x4>;
133 reg-shift = <0x2>;
134 interrupt-parent = <&periph_intc>;
142 reg = <0x406b80 0x20>;
143 reg-io-width = <0x4>;
144 reg-shift = <0x2>;
145 interrupt-parent = <&periph_intc>;
152 clock-frequency = <390000>;
153 compatible = "brcm,brcmstb-i2c";
154 interrupt-parent = <&upg_irq0_intc>;
155 reg = <0x406200 0x58>;
157 interrupt-names = "upg_bsca";
162 clock-frequency = <390000>;
163 compatible = "brcm,brcmstb-i2c";
164 interrupt-parent = <&upg_irq0_intc>;
165 reg = <0x406280 0x58>;
167 interrupt-names = "upg_bscb";
172 clock-frequency = <390000>;
173 compatible = "brcm,brcmstb-i2c";
174 interrupt-parent = <&upg_irq0_intc>;
175 reg = <0x406300 0x58>;
177 interrupt-names = "upg_bscc";
182 clock-frequency = <390000>;
183 compatible = "brcm,brcmstb-i2c";
184 interrupt-parent = <&upg_irq0_intc>;
185 reg = <0x406380 0x58>;
187 interrupt-names = "upg_bscd";
192 clock-frequency = <390000>;
193 compatible = "brcm,brcmstb-i2c";
194 interrupt-parent = <&upg_irq0_intc>;
195 reg = <0x406800 0x58>;
197 interrupt-names = "upg_bsce";
202 compatible = "brcm,bcm7038-pwm";
203 reg = <0x406580 0x28>;
204 #pwm-cells = <2>;
210 compatible = "brcm,bcm7038-pwm";
211 reg = <0x406880 0x28>;
212 #pwm-cells = <2>;
219 compatible = "brcm,bcm7038-wdt";
220 reg = <0x4067e8 0x14>;
225 compatible = "brcm,brcmstb-gpio";
226 reg = <0x406700 0x80>;
227 #gpio-cells = <2>;
228 #interrupt-cells = <2>;
229 gpio-controller;
230 interrupt-controller;
231 interrupt-parent = <&upg_irq0_intc>;
233 brcm,gpio-bank-widths = <32 32 32 27>;
237 phy-mode = "internal";
238 phy-handle = <&phy1>;
239 mac-address = [ 00 10 18 36 23 1a ];
240 compatible = "brcm,genet-v1";
241 #address-cells = <0x1>;
242 #size-cells = <0x1>;
243 reg = <0x468000 0x3c8c>;
245 interrupt-parent = <&periph_intc>;
249 compatible = "brcm,genet-mdio-v1";
250 #address-cells = <0x1>;
251 #size-cells = <0x0>;
252 reg = <0xe14 0x8>;
254 phy1: ethernet-phy@1 {
255 max-speed = <100>;
256 reg = <0x1>;
257 compatible = "brcm,65nm-ephy",
258 "ethernet-phy-ieee802.3-c22";
264 compatible = "brcm,bcm7420-ehci", "generic-ehci";
265 reg = <0x488300 0x100>;
266 interrupt-parent = <&periph_intc>;
272 compatible = "brcm,bcm7420-ohci", "generic-ohci";
273 reg = <0x488400 0x100>;
274 native-endian;
275 no-big-frame-no;
276 interrupt-parent = <&periph_intc>;
282 compatible = "brcm,bcm7420-ehci", "generic-ehci";
283 reg = <0x488500 0x100>;
284 interrupt-parent = <&periph_intc>;
290 compatible = "brcm,bcm7420-ohci", "generic-ohci";
291 reg = <0x488600 0x100>;
292 native-endian;
293 no-big-frame-no;
294 interrupt-parent = <&periph_intc>;
299 spi_l2_intc: interrupt-controller@411d00 {
300 compatible = "brcm,l2-intc";
301 reg = <0x411d00 0x30>;
302 interrupt-controller;
303 #interrupt-cells = <1>;
304 interrupt-parent = <&periph_intc>;
309 #address-cells = <0x1>;
310 #size-cells = <0x0>;
311 compatible = "brcm,spi-bcm-qspi",
312 "brcm,spi-brcmstb-qspi";
314 reg = <0x440920 0x4 0x443200 0x188 0x443000 0x50>;
315 reg-names = "cs_reg", "hif_mspi", "bspi";
317 interrupt-parent = <&spi_l2_intc>;
318 interrupt-names = "spi_lr_fullness_reached",
329 #address-cells = <1>;
330 #size-cells = <0>;
331 compatible = "brcm,spi-bcm-qspi",
332 "brcm,spi-brcmstb-mspi";
334 reg = <0x406400 0x180>;
335 reg-names = "mspi";
337 interrupt-parent = <&upg_irq0_intc>;
338 interrupt-names = "mspi_done";