Lines Matching +full:loongson +full:- +full:3
1 # SPDX-License-Identifier: GPL-2.0
124 bool "Generic board-agnostic MIPS kernel"
211 Support for the Texas Instruments AR7 System-on-a-Chip
282 Build a generic DT-based kernel image that boots on select
283 BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
373 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
374 DECstation porting pages on <http://decstation.unix-ag.org/>.
413 Olivetti M700-10 workstations.
447 bool "Loongson 32-bit family of machines"
450 This enables support for the Loongson-1 family of machines.
452 Loongson-1 is a family of 32-bit MIPS-compatible SoCs developed by
457 bool "Loongson-2E/F family of machines"
460 This enables the support of early Loongson-2E/F family of machines.
463 bool "Loongson 64-bit family of machines"
498 This enables the support of Loongson-2/3 family of machines.
500 Loongson-2 and Loongson-3 are 64-bit general-purpose processors with
501 GS264/GS464/GS464E/GS464V microarchitecture (except old Loongson-2E
502 and Loongson-2F which will be removed), developed by the Institute
597 Microchip PIC32 is a family of general-purpose 32 bit MIPS core
784 bool "Sibyte BCM91120C-CRhine"
793 bool "Sibyte BCM91120x-Carmel"
802 bool "Sibyte BCM91125C-CRhone"
812 bool "Sibyte BCM91125E-Rhone"
821 bool "Sibyte BCM91250A-SWARM"
834 bool "Sibyte BCM91250C2-LittleSur"
846 bool "Sibyte BCM91250E-Sentosa"
856 bool "Sibyte BCM91480B-BigSur"
905 The SNI RM200/300/400 are MIPS-based machines manufactured by
1047 source "arch/mips/sgi-ip27/Kconfig"
1051 source "arch/mips/cavium-octeon/Kconfig"
1364 bool "Loongson 64-bit CPU"
1384 The Loongson GSx64(GS264/GS464/GS464E/GS464V) series of processor
1386 including most 64-bit Loongson-2 (2H, 2K) and Loongson-3 (3A1000,
1387 3B1000, 3B1500, 3A2000, 3A3000 and 3A4000) processors. However, old
1388 Loongson-2E/2F is not covered here and will be removed in future.
1391 bool "New Loongson-3 CPU Enhancements"
1395 New Loongson-3 cores (since Loongson-3A R2, as opposed to Loongson-3A
1396 R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
1397 FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPr2 ASE, User
1398 Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
1402 time. If you want a generic kernel to run on all Loongson 3 machines,
1403 please say 'N' here. If you want a high-performance kernel to run on
1404 new Loongson-3 machines only, please say 'Y' here.
1407 bool "Old Loongson-3 LLSC Workarounds"
1411 Loongson-3 processors have the llsc issues which require workarounds.
1414 Newer Loongson-3 will fix these issues and no workarounds are needed.
1422 bool "Emulate the CPUCFG instruction on older Loongson cores"
1426 Loongson-3A R4 and newer have the CPUCFG instruction available for
1428 option provides emulation of the instruction on older Loongson
1429 cores, back to Loongson-3A1000.
1434 bool "Loongson 2E"
1438 The Loongson 2E processor implements the MIPS III instruction set
1445 bool "Loongson 2F"
1450 The Loongson 2F processor implements the MIPS III instruction set
1453 Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
1458 bool "Loongson 1B"
1463 The Loongson 1B is a 32-bit SoC, which implements the MIPS32
1468 bool "Loongson 1C"
1473 The Loongson 1C is a 32-bit SoC, which implements the MIPS32
1485 MIPS32 architecture. Most modern embedded systems with a 32-bit
1504 MIPS32 architecture. Most modern embedded systems with a 32-bit
1550 MIPS64 architecture. Many modern embedded systems with a 64-bit
1571 MIPS64 architecture. Many modern embedded systems with a 64-bit
1626 MMU with two-levels TLB, UCA, MSA, MDU core level features and system
1628 cache, IOCU/IOMMU (though might be unused depending on the system-
1671 MIPS Technologies R4000-series processors other than 4300, including
1689 MIPS Technologies R5000-series processors other than the Nevada.
1698 NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
1708 QED / PMC-Sierra RM52xx-series ("Nevada") processors.
1719 MIPS Technologies R10000-series processors.
1824 of lowmem (up to 3GB). If unsure, say 'N' here.
1850 64-bit addressing which in turn makes the PTEs 64-bit in size.
1861 bool "Loongson 2F Workarounds"
1866 Loongson 2F01 / 2F02 processors have the NOP & JUMP issues which
1869 -mfix-loongson2f-nop and -mfix-loongson2f-jump options.
1871 Loongson 2F03 and later have fixed these issues and no workarounds
2053 # CPU may reorder R->R, R->W, W->R, W->W
2061 # CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC
2160 actually benefits from 64-bit processing or if your machine has
2162 menu if your system does not support both 32-bit and 64-bit kernels.
2165 bool "32-bit kernel"
2169 Select this option if you want to build a 32-bit kernel.
2172 bool "64-bit kernel"
2175 Select this option if you want to build a 64-bit kernel.
2192 Set this to non-zero if building a guest kernel for KVM to skip RTC
2218 R3000-family processors this is the only available page size. Using
2238 all non-R3000 family processors. Note that you will need a suitable
2257 all non-R3000 family processor. Not that at the time of this
2294 # Support for a MIPS32 / MIPS64 style S-caches
2373 <http://www.imgtec.com/mips/mips-multithreading.asp>.
2394 bool "Dynamic FPU affinity for FP-intensive threads"
2399 bool "MIPS R2-to-R6 emulator"
2404 Choose this option if you want to run non-R6 MIPS userland code.
2407 The only reason this is a build-time option is to save ~14K from the
2603 # CPU non-features
2638 # interrupts during indexed I-cache flushes seems to be sufficient to deal
2690 # The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
2692 # I-cache line worth of instructions being fetched may case spurious
2698 # may cause ll / sc and lld / scd sequences to execute non-atomically.
2707 # - Highmem only makes sense for the 32-bit kernel.
2708 # - The current highmem code will only work properly on physically indexed
2715 # - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we
2738 This option must be set if a kernel might be executed on a MIPS16-
2740 words, it makes the kernel MIPS16-tolerant.
2757 Say Y to compile the kernel to support NUMA (Non-Uniform Memory
2830 This is limited by the size of KSEG0, 256Mb on 32-bit or 1Gb with
2831 EVA or 64-bit. The default is 16Mb.
2858 bool "Multi-Processing support"
2865 If you say N here, the kernel will run on uni- and multiprocessor
2874 See also the SMP-HOWTO available at
2880 bool "Support for hot-pluggable CPUs"
2917 int "Maximum number of CPUs (2-256)"
2927 kernel will support. The maximum supported value is 32 for 32-bit
2928 kernel and 64 for 64-bit kernels; the minimum value which makes
2932 This is purely to save memory - each supported CPU adds
3056 which are loaded in the main kernel with kexec-tools into
3071 passed to the panic-ed kernel).
3074 bool "Support for O32 binaries using 64-bit FP" if !CPU_MIPSR6
3077 When this is enabled, the kernel will support use of 64-bit floating
3079 EF_MIPS_FP64 ELF header flag (typically built with -mfp64). On
3080 32-bit MIPS systems this support is at the cost of increasing the
3083 will require 64-bit floating point, you may wish to reduce the size
3125 objcopy --update-section .appended_dtb=<filename>.dtb vmlinux
3185 default 3 if 64BIT && !PAGE_SIZE_64KB
3219 <http://www.computer-refuge.org/classiccmp/ftp.digital.com/pub/DEC/TriAdd/>
3221 <http://www.linux-mips.org/wiki/DECstation>
3276 32-bit binaries as used by the 32-bit Linux/MIPS port. Most of
3290 64-bit binaries using 32-bit quantities for addressing and certain
3291 data that would normally be 64-bit. They are used in special