microblaze/kernel/hw_exception_handler.S

3  * Exception handling for Microblaze
18  *		Low-level exception handers, MMU support, and rewrite.
45  * Microblaze HW Exception Handler
46  * - Non self-modifying exception handler for the following exception conditions
53  *   - Privileged instruction exception (MMU)
54  *   - Data storage exception (MMU)
55  *   - Instruction storage exception (MMU)
56  *   - Data TLB miss exception (MMU)
57  *   - Instruction TLB miss exception (MMU)
59  * Note we disable interrupts during exception handling, otherwise we will
198 .extern other_exception_handler /* Defined in exception.c */
203  * Exception handler notes:
240  * MMU exception handler has different handling compare to no MMU kernel.
241  * Exception handler use jump table for directing of what happen. For MMU kernel
242  * is this approach better because MMU relate exception are handled by asm code
243  * in this file. In compare to with MMU expect of unaligned exception
250  * return from exception
261 /* Create space for exception counting. */
266 	/* Look at exception vector table. There is 32 exceptions * word size */
275 /*  1 - Unaligned data access exception */
277 /*  2 - Illegal op-code exception */
279 /*  3 - Instruction bus error exception */
281 /*  4 - Data bus error exception */
283 /*  5 - Divide by zero exception */
285 /*  6 - Floating point unit exception */
287 /*  7 - Privileged instruction exception */
298 /* 16 - Data storage exception */
300 /* 17 - Instruction storage exception */
302 /* 18 - Data TLB miss exception */
304 /* 19 - Instruction TLB miss exception */
365 	/* Calculate exception vector offset = r5 << 2 */
370 /* counting which exception happen */
379 	/* Load the HW Exception vector */
396 	xori	r6, r5, 1; /* 00001 = Unaligned Exception */
397 	/* Jump to unalignment exception handler */
418 	addk	r8, r17, r0; /* Load exception address */
451 	bri	ex_handler_done; /* Complete exception handling */
454 /* 0x01 - Unaligned data access exception
490 	lbui	r5, r3, 0; /* Exception address in r3 */
504 	lbui	r5, r3, 0; /* Exception address in r3 */
522 ex_lw_end: /* Exception handling of load word, ends */
558 ex_sw_end: /* Exception handling of store word, ends. */
580 	/* Exception vector entry code. This code runs with address translation
583 	/* Exception vectors. */
585 	/* 0x10 - Data Storage Exception
681 		/* The bailout. Restore registers to pre-exception conditions
690 	/* 0x11 - Instruction Storage Exception
700 	/* 0x12 - Data TLB Miss Exception
762 		/* The bailout. Restore registers to pre-exception conditions
771 	/* 0x13 - Instruction TLB Miss Exception
833 		/* The bailout. Restore registers to pre-exception conditions
933 /* Unaligned data access exception last on a 4k page for MMU.
953 load1:	lbui	r5, r4, 0;	/* Exception address in r4 - delay slot */
978 ex_lw_end_vm:			/* Exception handling of load word, ends */
1014 ex_sw_end_vm:			/* Exception handling of store word, ends. */
1027 	 * in PT_PC which is used as return address from exception */
1051 /* FIXME add handle function for unhandled exception - dump register */
1056  * - Contains code snippets for each register that caused the unalign exception
1057  * - Hence exception handler is NOT self-modifying