Lines Matching +full:0 +full:xfffffe00
311 TC_ENABLE = 0x8000
312 TC_PAGE8K = 0x4000
313 TC_PAGE4K = 0x0000
316 TTR_ENABLE = 0x8000 /* enable transparent translation */
317 TTR_ANYMODE = 0x4000 /* user and kernel mode access */
318 TTR_KERNELMODE = 0x2000 /* only kernel mode access */
319 TTR_USERMODE = 0x0000 /* only user mode access */
320 TTR_CI = 0x0400 /* inhibit cache */
321 TTR_RW = 0x0200 /* read/write mode */
322 TTR_RWM = 0x0100 /* read/write mask */
323 TTR_FCB2 = 0x0040 /* function code base bit 2 */
324 TTR_FCB1 = 0x0020 /* function code base bit 1 */
325 TTR_FCB0 = 0x0010 /* function code base bit 0 */
326 TTR_FCM2 = 0x0004 /* function code mask bit 2 */
327 TTR_FCM1 = 0x0002 /* function code mask bit 1 */
328 TTR_FCM0 = 0x0001 /* function code mask bit 0 */
331 CC6_ENABLE_D = 0x80000000 /* enable data cache (680[46]0) */
332 CC6_FREEZE_D = 0x40000000 /* freeze data cache (68060) */
333 CC6_ENABLE_SB = 0x20000000 /* enable store buffer (68060) */
334 CC6_PUSH_DPI = 0x10000000 /* disable CPUSH invalidation (68060) */
335 CC6_HALF_D = 0x08000000 /* half-cache mode for data cache (68060) */
336 CC6_ENABLE_B = 0x00800000 /* enable branch cache (68060) */
337 CC6_CLRA_B = 0x00400000 /* clear all entries in branch cache (68060) */
338 CC6_CLRU_B = 0x00200000 /* clear user entries in branch cache (68060) */
339 CC6_ENABLE_I = 0x00008000 /* enable instruction cache (680[46]0) */
340 CC6_FREEZE_I = 0x00004000 /* freeze instruction cache (68060) */
341 CC6_HALF_I = 0x00002000 /* half-cache mode for instruction cache (68060) */
342 CC3_ALLOC_WRITE = 0x00002000 /* write allocate mode(68030) */
343 CC3_ENABLE_DB = 0x00001000 /* enable data burst (68030) */
344 CC3_CLR_D = 0x00000800 /* clear data cache (68030) */
345 CC3_CLRE_D = 0x00000400 /* clear entry in data cache (68030) */
346 CC3_FREEZE_D = 0x00000200 /* freeze data cache (68030) */
347 CC3_ENABLE_D = 0x00000100 /* enable data cache (68030) */
348 CC3_ENABLE_IB = 0x00000010 /* enable instruction burst (68030) */
349 CC3_CLR_I = 0x00000008 /* clear instruction cache (68030) */
350 CC3_CLRE_I = 0x00000004 /* clear entry in instruction cache (68030) */
351 CC3_FREEZE_I = 0x00000002 /* freeze instruction cache (68030) */
352 CC3_ENABLE_I = 0x00000001 /* enable instruction cache (68030) */
407 .macro func_start name,saveregs,stack=0
435 .macro func_define name,nr=0
582 .long 0
617 leds 0x1
749 movew #0x2700,%sr
758 phys. 0x0. This should result in a bus error on all other machines.
761 same behaviour (0x0..0x7 are no ROM shadow). So we have to do
763 read attempt for 0x00ff82fe phys. that should bus error on a Falcon
766 The test for the Hades is done by reading address 0xb0000000. This
774 moveq #0,%d3 /* default if tag doesn't exist */
783 * serial port. There are no I/O regs at 0x00ffxxxx at all. */
784 moveq #0,%d0
787 movel #0xff000000,%d0 /* Hades I/O base addr: 0xff000000 */
826 .word 0x70 /* trap 0x70 - .BRD_ID */
887 leds 0x2
904 leds 0x4
945 * 040: Map the 16Meg range physical 0x0 up to logical 0x8000.0000
947 mmu_map #0x80000000,#0,#0x01000000,#_PAGE_NOCACHE_S
952 mmu_map_tt #1,#0x40000000,#0x20000000,#_PAGE_NOCACHE_S
958 * 030: Map the 32Meg range physical 0x0 up to logical 0x8000.0000
960 mmu_map #0x80000000,#0,#0x02000000,#_PAGE_NOCACHE030
961 mmu_map_tt #1,#0x40000000,#0x20000000,#_PAGE_NOCACHE030
976 /* On the Atari, we map the I/O region (phys. 0x00ffxxxx) by mapping
978 0xffxxxxxx -> 0x00xxxxxx). For this, an additional pointer table is
982 (i.e. 0xffxxxxxx -> 0xffxxxxxx), because some I/O registers are
989 /* I/O base addr for non-Medusa, non-Hades: 0x00000000 */
990 moveq #0,%d0
996 2: movel #0xff000000,%d0 /* Medusa/Hades base addr: 0xff000000 */
1002 * need to disable caches (crucial only for 0xff8000..0xffffff
1003 * (standard I/O) and 0xf00000..0xf3ffff (IDE)). The remainder
1005 * ROMs (mirror at phys. 0x0), so caching isn't necessary for
1007 mmu_map #0xff000000,%d3,#0x01000000,#_PAGE_NOCACHE030
1013 mmu_map #0xff000000,%d3,#0x01000000,#_PAGE_NOCACHE_S
1023 * add transparent mapping for 0xff00 0000 - 0xffff ffff
1026 * 0xfe000000-0xfeffffff is for screen and ROM
1031 mmu_map_tt #0,#0xfe000000,#0x01000000,#_PAGE_CACHE040W
1032 mmu_map_tt #1,#0xff000000,#0x01000000,#_PAGE_NOCACHE_S
1042 /* On the HP300, we map the ROM, INTIO and DIO regions (phys. 0x00xxxxxx)
1043 * by mapping 32MB (on 020/030) or 16 MB (on 040) from 0xf0xxxxxx -> 0x00xxxxxx).
1050 * 030: Map the 32Meg range physical 0x0 up to logical 0xf000.0000
1052 mmu_map #0xf0000000,#0,#0x02000000,#_PAGE_NOCACHE030
1058 * 040: Map the 16Meg range physical 0x0 up to logical 0xf000.0000
1060 mmu_map #0xf0000000,#0,#0x01000000,#_PAGE_NOCACHE_S
1073 * 4MB of RAM at address 0, so now need to do a transparent
1078 mmu_map_tt #1,#0xe0000000,#0x20000000,#_PAGE_NOCACHE030
1091 * 4MB of RAM at address 0, so now need to do a transparent
1097 * IO is in the range 0xfff00000 to 0xfffeffff.
1098 * PROM is 0xff800000->0xffbfffff and SRAM is
1099 * 0xffe00000->0xffe1ffff.
1102 mmu_map_tt #1,#0xe0000000,#0x20000000,#_PAGE_NOCACHE_S
1115 * 4MB of RAM at address 0, so now need to do a transparent
1122 mmu_map_tt #1,#0xe0000000,#0x20000000,#_PAGE_NOCACHE_S
1141 * 0x5000.0000 ... 0x5300.0000 range,
1145 * 0x0000.0000 then we know there is valid RAM just
1148 * By the way, if the frame buffer is at 0x0000.0000
1173 * Mac Note: screen address of logical 0xF000.0000 -> <screen physical>
1182 mmu_map_eq #0x40000000,#0x02000000,%d3
1184 mmu_map_eq #0x50000000,#0x03000000,%d3
1185 /* Nubus slot space (video at 0xF0000000, rom at 0xF0F80000) */
1186 mmu_map_tt #1,#0xf8000000,#0x08000000,%d3
1201 /* copy maps from 0xfee00000 to 0xff000000 */
1202 movel #0xfee00000, %d0
1207 movel #0xfee00000, %d0
1213 movel #0xfee00000, %d0
1220 movel 0xfefe00d4, %a1
1223 movel #((0x200000 >> 13)-1), %d1
1228 addl #0x1000,%d3
1234 mmu_map_tt #1,#0x40000000,#0x40000000,#_PAGE_NOCACHE_S
1244 mmu_map #0x80000000,#0,#0x02000000,#_PAGE_NOCACHE030
1253 leds 0x8
1327 * the logical memory for the kernel, i.e., 0x01000.
1328 * B. The kernel is located some where else. e.g., 0x0400.0000
1339 * then create a mapping for the kernel at logical 0x8000.0000 to
1342 * is engaged, the PC can be moved up into the 0x8000.0000 range
1348 * is made in page 0 (an as of yet unused location -- except for the
1356 * Last, if _start is already at 0x01000, then there's nothing special
1387 movel #0xff000000,L(iobase)
1403 orl #0x50000000,L(mac_sccbase)
1412 movel #0xf0000000,L(iobase)
1418 movel #0x60,0xf05f400c
1424 1: movew #0,0xf05f400e
1425 movew #0x64,0xf05f400e
1433 oriw #0x4000,0x61000000
1443 movel #0x80000000,L(iobase)
1448 leds 0x10
1509 leds 0x55
1529 2: moveq #0,%d0
1585 * bits 11..0 - offset into a particular 4K page
1612 #define mmu_next_valid 0
1620 #define MMU_PRINT_UNINITED 0
1637 #if 0
1645 #if 0
1657 andil #0xFFFFFE00,%d7
1669 andil #0xFFFFFF00,%d7
1677 btst #0,%d6
1704 movel #0x00000000,%a4 /* logical address */
1705 moveql #0,%d0
1716 movel #0,%d1
1717 andil #0xfffffe00,%d6
1728 movel #0,%d2
1729 andil #0xffffff00,%d6
1735 btst #0,%d6
1743 andil #0xfffff4e0,%d1
1766 andiw #0x8000,%d1 /* is it valid ? */
1770 andil #0xff000000,%d1 /* Get the address */
1780 andiw #0x8000,%d1 /* is it valid ? */
1784 andil #0xff000000,%d1 /* Get the address */
1826 andil #0xfffffff0,%d0
1828 movel #0x00000000,%a4 /* logical address */
1829 movel #0,%d0
1836 btst #0,%d6 /* is it early terminating? */
1844 movel #0,%d1
1845 andil #0xfffffff0,%d6
1853 btst #0,%d6 /* is it a page descriptor? */
1861 movel #0,%d2
1862 andil #0xfffffff0,%d6
1868 btst #0,%d6
1973 puts "cputype: 0"
1982 9: putc '0'
2010 bfffo ARG3{#0,#32},%d1
2387 alignment restriction for pointer tables on the '0[46]0. */
2485 movel #0x80000002,%a0@
2487 movel #0x0808,%d0
2495 movel #0x82c07760,%a0@(8)
2499 movel #0x0808,%d0
2517 #if 0
2574 #if 0
2585 #if 0
2635 #if 0
2645 #if 0
2689 #if 0
2740 .byte 4,0x44 /* x16, 1 stopbit, no parity */
2741 .byte 3,0xc0 /* receiver: 8 bpc */
2742 .byte 5,0xe2 /* transmitter: 8 bpc, assert dtr/rts */
2743 .byte 10,0 /* NRZ */
2744 .byte 11,0x50 /* use baud rate generator */
2745 .byte 12,1,13,0 /* 38400 baud */
2747 .byte 3,0xc1 /* enable receiver */
2748 .byte 5,0xea /* enable transmitter */
2764 .byte 4,0x44 /* x16, 1 stopbit, no parity */
2765 .byte 3,0xc0 /* receiver: 8 bpc */
2766 .byte 5,0xe2 /* transmitter: 8 bpc, assert dtr/rts */
2767 .byte 10,0 /* NRZ */
2768 .byte 11,0x50 /* use baud rate generator */
2769 .byte 12,24,13,0 /* 9600 baud */
2771 .byte 3,0xc1 /* enable receiver */
2772 .byte 5,0xea /* enable transmitter */
2779 LPSG_SELECT = 0xff8800
2780 LPSG_READ = 0xff8800
2781 LPSG_WRITE = 0xff8802
2785 LSTMFP_GPIP = 0xfffa01
2786 LSTMFP_DDR = 0xfffa05
2787 LSTMFP_IERB = 0xfffa09
2791 LSCC_CTRL = 0xff8c85
2792 LSCC_DATA = 0xff8c87
2796 LSCC_CTRL = 0xff8c81
2797 LSCC_DATA = 0xff8c83
2801 LMFP_UCR = 0xfffa29
2802 LMFP_TDCDR = 0xfffa1d
2803 LMFP_TDDR = 0xfffa25
2804 LMFP_TSR = 0xfffa2d
2805 LMFP_UDR = 0xfffa2f
2851 bclr #0,%a1@(LSTMFP_IERB)
2852 bclr #0,%a1@(LSTMFP_DDR)
2854 moveb #0xff,%a1@(LPSG_WRITE)
2867 moveb #0xc0,%a0@
2884 moveb #0x88,%a1@(LMFP_UCR)
2885 andb #0x70,%a1@(LMFP_TDCDR)
2897 #define mac_scc_cha_b_ctrl_offset 0x0
2898 #define mac_scc_cha_a_ctrl_offset 0x2
2899 #define mac_scc_cha_b_data_offset 0x4
2900 #define mac_scc_cha_a_data_offset 0x6
2906 moveb #0xc0,%a0@(mac_scc_cha_a_ctrl_offset)
2943 move.l #0xff020010,%a1@ /* must be inited - also used by debug=mem */
2944 move.l #0xff020000,%a1
2959 /*nodbg: q40_do_debug is 0 by default*/
2965 moveb #0x10,M167_PCSCCMICR
2966 moveb #0x10,M167_PCSCCTICR
2967 moveb #0x10,M167_PCSCCRICR
2998 andw #0x00ff,%d0
2999 oriw #0x0100,%d0
3003 andw #0x2000,%d0
3032 3: btst #0,%a1@(LSTMFP_GPIP)
3096 moveb #0,M167_CYCAR
3098 moveb #0x02,M167_CYIER
3105 moveb #0x08,M167_CYTEOIR
3109 moveb #0,M167_CYTEOIR
3115 .word 0x0020 /* TRAP 0x020 */
3137 movel 0xFEFE0018,%a1
3162 andb #0x4,%d0
3177 andb #0x20,%d1
3182 andb #0x20,%d1
3223 andb #0x0f,%d2
3224 addb #'0',%d2
3254 ori #0x0700,%sr
3281 moveb %d0,%a0@(0x1ffff)
3288 eorw #0xff00,%d0
3300 #define Lconsole_struct_cur_column 0
3327 andl #0xffff,%d3 /* d3 = screen width in pixels */
3328 andl #0xffff,%d4 /* d4 = screen height in pixels */
3353 lea 0,%a0
3407 andil #0xffff,%d0
3460 andl #0xffff,%d3 /* d3 = screen width in pixels */
3461 andl #0xffff,%d4 /* d4 = screen height in pixels */
3577 andl #0x000000ff,%d7
3586 * d2 = (bit 0) 1/0 for white/black (!) pixel on screen
3622 * d2 = (bit 0) 1/0 for white/black (!)
3638 * d2 = black or white (0/1)
3718 moveb #0xff,%a1@
3735 movew #0x0fff,%a1@
3747 .long 0
3753 .long 0
3758 .long 0 /* cursor column */
3759 .long 0 /* cursor row */
3760 .long 0 /* max num columns */
3761 .long 0 /* max num rows */
3762 .long 0 /* left edge */
3764 .long 0 /* pointer to console font (struct font_desc) */
3766 .long 0 /* pointer to console font data */
3771 .long 0 /* valid flag */
3772 .long 0 /* start logical */
3773 .long 0 /* next logical */
3774 .long 0 /* start physical */
3775 .long 0 /* next physical */
3779 .long 0
3781 .long 0
3783 .long 0
3785 .long 0
3787 .long 0
3789 .long 0
3791 .long 0
3793 .long 0
3796 M147_SCC_CTRL_A = 0xfffe3002
3797 M147_SCC_DATA_A = 0xfffe3003
3801 M162_SCC_CTRL_A = 0xfff45005
3802 M167_CYCAR = 0xfff450ee
3803 M167_CYIER = 0xfff45011
3804 M167_CYLICR = 0xfff45026
3805 M167_CYTEOIR = 0xfff45085
3806 M167_CYTDR = 0xfff450f8
3807 M167_PCSCCMICR = 0xfff4201d
3808 M167_PCSCCTICR = 0xfff4201e
3809 M167_PCSCCRICR = 0xfff4201f
3810 M167_PCTPIACKR = 0xfff42025
3814 BVME_SCC_CTRL_A = 0xffb0000b
3815 BVME_SCC_DATA_A = 0xffb0000f
3820 .long 0
3822 .long 0
3824 .long 0
3826 .long 0
3828 .long 0
3832 LSRB0 = 0x10412
3833 LTHRB0 = 0x10416
3834 LCPUCTRL = 0x10100
3838 DCADATA = 0x11
3839 DCALSR = 0x1b
3840 APCIDATA = 0x00
3841 APCILSR = 0x14
3843 .long 0
3853 .long 0
3855 .long 0
3857 .long 0
3860 .long 0,0,0,0,0,0,0,0
3864 .long 0
3866 .long 0