Lines Matching +full:0 +full:x00000060

24 #define CACR_EC		0x80000000	/* Enable cache */
25 #define CACR_ESB	0x20000000	/* Enable store buffer */
26 #define CACR_DPI	0x10000000	/* Disable invalidation by CPUSHL */
27 #define CACR_HLCK	0x08000000	/* Half cache lock mode */
28 #define CACR_CINVA	0x01000000	/* Invalidate cache */
29 #define CACR_DNFB	0x00000400	/* Inhibited fill buffer */
30 #define CACR_DCM_WT	0x00000000	/* Cacheable write-through */
31 #define CACR_DCM_CB	0x00000100	/* Cacheable copy-back */
32 #define CACR_DCM_PRE	0x00000200	/* Cache inhibited, precise */
33 #define CACR_DCM_IMPRE	0x00000300	/* Cache inhibited, imprecise */
34 #define CACR_WPROTECT	0x00000020	/* Write protect*/
35 #define CACR_EUSP	0x00000010	/* Eanble separate user a7 */
42 #define ACR_ENABLE	0x00008000	/* Enable this ACR */
43 #define ACR_USER	0x00000000	/* Allow only user accesses */
44 #define ACR_SUPER	0x00002000	/* Allow supervisor access only */
45 #define ACR_ANY		0x00004000	/* Allow any access type */
46 #define ACR_CM_WT	0x00000000	/* Cacheable, write-through */
47 #define ACR_CM_CB	0x00000020	/* Cacheable, copy-back */
48 #define ACR_CM_PRE	0x00000040	/* Cache inhibited, precise */
49 #define ACR_CM_IMPRE	0x00000060	/* Cache inhibited, imprecise */
50 #define ACR_WPROTECT	0x00000004	/* Write protect region */
56 #define	CACHE_SIZE	0x2000		/* 8k of unified cache */
60 #define	CACHE_SIZE	0x4000		/* 16k of unified cache */
96 #define ACR0_MODE	((CONFIG_RAMBASE & 0xff000000) + \
97 			 (0x000f0000) + \
99 #define ACR1_MODE	0