Lines Matching +full:imx1 +full:- +full:ccm
1 // SPDX-License-Identifier: GPL-2.0
3 * m5441x.c -- support for Coldfire m5441x processors
23 DEFINE_CLK(0, "imx1-i2c.1", 14, MCF_CLK);
29 DEFINE_CLK(0, "imx1-i2c.0", 22, MCF_CLK);
30 DEFINE_CLK(0, "fsl-dspi.0", 23, MCF_CLK);
48 DEFINE_CLK(0, "mcfusb-otg.0", 44, MCF_CLK);
49 DEFINE_CLK(0, "mcfusb-host.0", 45, MCF_CLK);
50 DEFINE_CLK(0, "mcfddr-sram.0", 46, MCF_CLK);
55 DEFINE_CLK(0, "sdhci-esdhc-mcf.0", 51, MCF_CLK);
56 DEFINE_CLK(0, "enet-fec.0", 53, MCF_CLK);
57 DEFINE_CLK(0, "enet-fec.1", 54, MCF_CLK);
63 DEFINE_CLK(1, "imx1-i2c.2", 4, MCF_CLK);
64 DEFINE_CLK(1, "imx1-i2c.3", 5, MCF_CLK);
65 DEFINE_CLK(1, "imx1-i2c.4", 6, MCF_CLK);
66 DEFINE_CLK(1, "imx1-i2c.5", 7, MCF_CLK);
165 &__clk_1_36, /* CCM/reset module/Power management */
189 &__clk_0_53, /* enet-fec */
190 &__clk_0_54, /* enet-fec */
194 &__clk_1_2, /* 1-wire */
209 __raw_writel(__raw_readl(MCFSDHC_CLK) | (1 << clk->slot), MCFSDHC_CLK); in __clk_enable2()
214 __raw_writel(__raw_readl(MCFSDHC_CLK) & ~(1 << clk->slot), MCFSDHC_CLK); in __clk_disable2()