1 // SPDX-License-Identifier: GPL-2.0-only
15  * The configuration register may be used to enable (and disable in some
19  * will not be able to disable it.
57  * This describes a contiguous area of like control bits used to enable/disable
67 	u8  enable_only;	/* bits are write-once to enable only */
69 	u8  disable;		/* value used to disable device */  member
87 	u8  disable;		/* value indicating disabled state */  member
97 /* These are callbacks to SOC-specific code. */
175 		dscr_write_locked1(reg, val, lock->lockreg, lock->key);  in dscr_write()
185  * Drivers can use this interface to enable/disable SoC IP blocks.
203 	ctl = info->ctl;  in dscr_set_devstate()
204 	stat = info->stat;  in dscr_set_devstate()
209 	ctl_shift = ctl->shift + ctl->nbits * (id - ctl->start_id);  in dscr_set_devstate()
210 	ctl_mask = ((1 << ctl->nbits) - 1) << ctl_shift;  in dscr_set_devstate()
214 		ctl_val = ctl->enable << ctl_shift;  in dscr_set_devstate()
217 		if (ctl->enable_only)  in dscr_set_devstate()
219 		ctl_val = ctl->disable << ctl_shift;  in dscr_set_devstate()
227 	val = soc_readl(dscr.base + ctl->reg);  in dscr_set_devstate()
231 	dscr_write(ctl->reg, val);  in dscr_set_devstate()
238 	ctl_shift = stat->shift + stat->nbits * (id - stat->start_id);  in dscr_set_devstate()
241 		ctl_val = stat->enable;  in dscr_set_devstate()
243 		ctl_val = stat->disable;  in dscr_set_devstate()
246 		val = soc_readl(dscr.base + stat->reg);  in dscr_set_devstate()
248 		val &= ((1 << stat->nbits) - 1);  in dscr_set_devstate()
254  * Drivers can use this to reset RMII module.
266 	if (r->mask == 0)  in dscr_rmii_reset()
271 	val = soc_readl(dscr.base + r->reg);  in dscr_rmii_reset()
273 		dscr_write(r->reg, val | r->mask);  in dscr_rmii_reset()
275 		dscr_write(r->reg, val & ~(r->mask));  in dscr_rmii_reset()
287 	err = of_property_read_u32_array(node, "ti,dscr-devstat", &val, 1);  in dscr_parse_devstat()
299 	err = of_property_read_u32_array(node, "ti,dscr-silicon-rev", vals, 3);  in dscr_parse_silicon_rev()
309  * an ethernet MAC address. The "ti,dscr-mac-fuse-regs"
313  *	ti,dscr-mac-fuse-regs = <reg0 b3 b2 b1 b0
317  * b3-b0 positionally represent bytes within the fuse register.
319  * Allowable values for b3-b0 are:
322  *      1-6 = index+1 into c6x_fuse_mac[]
330 	err = of_property_read_u32_array(node, "ti,dscr-mac-fuse-regs",  in dscr_parse_mac_fuse()
337 		for (j = (f * 5) + 1, i = 24; i >= 0; i -= 8, j++)  in dscr_parse_mac_fuse()
339 				c6x_fuse_mac[vals[j] - 1] = fuse >> i;  in dscr_parse_mac_fuse()
350 	p = of_get_property(node, "ti,dscr-rmii-resets", &size);  in dscr_parse_rmii_resets()
352 		/* parse all the reg/mask pairs we can handle */  in dscr_parse_rmii_resets()
371 	err = of_property_read_u32_array(node, "ti,dscr-privperm", vals, 2);  in dscr_parse_privperm()
378  * SoCs may have "locked" DSCR registers which can only be written
380  * regisers can be described with the "ti,dscr-locked-regs" property.
384  *	ti,dscr-locked-regs = <reg0 lockreg0 key0
400 	p = of_get_property(node, "ti,dscr-locked-regs", &size);  in dscr_parse_locked_regs()
402 		/* parse all the register descriptions we can handle */  in dscr_parse_locked_regs()
410 			r->reg = be32_to_cpup(p++);  in dscr_parse_locked_regs()
411 			r->lockreg = be32_to_cpup(p++);  in dscr_parse_locked_regs()
412 			r->key = be32_to_cpup(p++);  in dscr_parse_locked_regs()
420  * and the key values can be parsed from a "ti,dscr-kick-regs"
423  *	ti,dscr-kick-regs = <kickreg0 key0 kickreg1 key1>
434 	err = of_property_read_u32_array(node, "ti,dscr-kick-regs", vals, 4);  in dscr_parse_kick_regs()
445  * SoCs may provide controls to enable/disable individual IP blocks. These
451  * The layout of these bitfields is described by the ti,dscr-devstate-ctl-regs
456  *   start_id num_ids reg enable disable start_bit nbits
462  * disable is the value to disable a device (0xffffffff if cannot disable)
473 	p = of_get_property(node, "ti,dscr-devstate-ctl-regs", &size);  in dscr_parse_devstate_ctl_regs()
475 		/* parse all the ranges we can handle */  in dscr_parse_devstate_ctl_regs()
483 			r->start_id = be32_to_cpup(p++);  in dscr_parse_devstate_ctl_regs()
484 			r->num_ids = be32_to_cpup(p++);  in dscr_parse_devstate_ctl_regs()
485 			r->reg = be32_to_cpup(p++);  in dscr_parse_devstate_ctl_regs()
486 			r->enable = be32_to_cpup(p++);  in dscr_parse_devstate_ctl_regs()
487 			r->disable = be32_to_cpup(p++);  in dscr_parse_devstate_ctl_regs()
488 			if (r->disable == 0xffffffff)  in dscr_parse_devstate_ctl_regs()
489 				r->enable_only = 1;  in dscr_parse_devstate_ctl_regs()
490 			r->shift = be32_to_cpup(p++);  in dscr_parse_devstate_ctl_regs()
491 			r->nbits = be32_to_cpup(p++);  in dscr_parse_devstate_ctl_regs()
493 			for (j = r->start_id;  in dscr_parse_devstate_ctl_regs()
494 			     j < (r->start_id + r->num_ids);  in dscr_parse_devstate_ctl_regs()
507  * The layout of these bitfields is described by the ti,dscr-devstate-stat-regs
512  *   start_id num_ids reg enable disable start_bit nbits
518  * disable is the value indicating device is disabled
529 	p = of_get_property(node, "ti,dscr-devstate-stat-regs", &size);  in dscr_parse_devstate_stat_regs()
531 		/* parse all the ranges we can handle */  in dscr_parse_devstate_stat_regs()
539 			r->start_id = be32_to_cpup(p++);  in dscr_parse_devstate_stat_regs()
540 			r->num_ids = be32_to_cpup(p++);  in dscr_parse_devstate_stat_regs()
541 			r->reg = be32_to_cpup(p++);  in dscr_parse_devstate_stat_regs()
542 			r->enable = be32_to_cpup(p++);  in dscr_parse_devstate_stat_regs()
543 			r->disable = be32_to_cpup(p++);  in dscr_parse_devstate_stat_regs()
544 			r->shift = be32_to_cpup(p++);  in dscr_parse_devstate_stat_regs()
545 			r->nbits = be32_to_cpup(p++);  in dscr_parse_devstate_stat_regs()
547 			for (j = r->start_id;  in dscr_parse_devstate_stat_regs()
548 			     j < (r->start_id + r->num_ids);  in dscr_parse_devstate_stat_regs()