Lines Matching +full:cpu +full:- +full:core
1 // SPDX-License-Identifier: GPL-2.0
4 #address-cells = <1>;
5 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 cpu@0 {
12 device_type = "cpu";
16 cpu@1 {
17 device_type = "cpu";
21 cpu@2 {
22 device_type = "cpu";
26 cpu@3 {
27 device_type = "cpu";
31 cpu@4 {
32 device_type = "cpu";
36 cpu@5 {
37 device_type = "cpu";
41 cpu@6 {
42 device_type = "cpu";
46 cpu@7 {
47 device_type = "cpu";
54 compatible = "simple-bus";
56 #address-cells = <1>;
57 #size-cells = <1>;
60 core_pic: interrupt-controller {
61 compatible = "ti,c64x+core-pic";
62 interrupt-controller;
63 #interrupt-cells = <1>;
66 megamod_pic: interrupt-controller@1800000 {
67 compatible = "ti,c64x+megamod-pic";
68 interrupt-controller;
69 #interrupt-cells = <1>;
71 interrupt-parent = <&core_pic>;
74 cache-controller@1840000 {
81 ti,core-mask = < 0x01 >;
87 ti,core-mask = < 0x02 >;
93 ti,core-mask = < 0x04 >;
99 ti,core-mask = < 0x08 >;
105 ti,core-mask = < 0x10 >;
111 ti,core-mask = < 0x20 >;
117 ti,core-mask = < 0x40 >;
123 ti,core-mask = < 0x80 >;
127 clock-controller@2310000 {
128 compatible = "ti,c6678-pll", "ti,c64x+pll";
130 ti,c64x+pll-bypass-delay = <200>;
131 ti,c64x+pll-reset-delay = <12000>;
132 ti,c64x+pll-lock-delay = <80000>;
135 device-state-controller@2620000 {
139 ti,dscr-devstat = <0x20>;
140 ti,dscr-silicon-rev = <0x18 28 0xf>;
142 ti,dscr-mac-fuse-regs = <0x110 1 2 3 4