arm64/kernel/entry.S

49 	.irp	n,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29
58 #define BAD_SYNC	0
66 	.if	\el == 0
87 	tbnz	x0, #THREAD_SHIFT, 0f
92 0:
145 	nop					// Patched to SMC/HVC #0
180 	stp	x0, x1, [sp, #16 * 0]
193 	stp	x26, x27, [sp, #16 * 13]
196 	.if	\el == 0
224 	/* No need to reset PSTATE.UAO, hardware's already set it to 0 for us */
225 	.endif /* \el == 0 */
235 	.if \el == 0
251 	.if	\el == 0
265 	SET_PSTATE_TCO(0)
280 	.if	\el != 0
308 	.if	\el == 0
330 	apply_ssbd 0, x0, x1
335 	ldp	x0, x1, [sp, #16 * 0]
348 	ldp	x26, x27, [sp, #16 * 13]
353 	.if	\el == 0
400 1:	and	x22, x22, #~PSR_PAN_BIT		// ARMv8.0 CPUs do not understand this bit
432 	ldr_this_cpu x25, irq_stack_ptr, x26
433 	mov	x26, #IRQ_STACK_SIZE
434 	add	x26, x25, x26
437 	mov	sp, x26
441 	adr_this_cpu scs_sp, irq_shadow_call_stack, x26
475 	 * Set res to 0 if irqs were unmasked in interrupted context.
476 	 * Otherwise set res to non-0 value.
524 	kernel_ventry	0, sync				// Synchronous 64-bit EL0
525 	kernel_ventry	0, irq				// IRQ 64-bit EL0
526 	kernel_ventry	0, fiq_invalid			// FIQ 64-bit EL0
527 	kernel_ventry	0, error			// Error 64-bit EL0
530 	kernel_ventry	0, sync_compat, 32		// Synchronous 32-bit EL0
531 	kernel_ventry	0, irq_compat, 32		// IRQ 32-bit EL0
532 	kernel_ventry	0, fiq_invalid_compat, 32	// FIQ 32-bit EL0
533 	kernel_ventry	0, error_compat, 32		// Error 32-bit EL0
535 	kernel_ventry	0, sync_invalid, 32		// Synchronous 32-bit EL0
536 	kernel_ventry	0, irq_invalid, 32		// IRQ 32-bit EL0
537 	kernel_ventry	0, fiq_invalid, 32		// FIQ 32-bit EL0
538 	kernel_ventry	0, error_invalid, 32		// Error 32-bit EL0
583 	inv_entry 0, BAD_SYNC
587 	inv_entry 0, BAD_IRQ
591 	inv_entry 0, BAD_FIQ
595 	inv_entry 0, BAD_ERROR
600 	inv_entry 0, BAD_FIQ, 32
652 	cbnz	x24, 1f				// preempt count != 0 || NMI return path
668 	kernel_entry 0
677 	kernel_entry 0, 32
685 	kernel_entry 0, 32
690 	kernel_entry 0, 32
697 	kernel_entry 0
722 	kernel_entry 0
755 	kernel_exit 0
851 	.space	0x400
899 	stp	x25, x26, [x8], #16
907 	ldp	x25, x26, [x8], #16
942 	smc	#0
944 99:	hvc	#0
1037 	stp     x26, x27, [x1, #SDEI_EVENT_INTREGS + 16 * 13]
1081 	and     x0, x3, #0xc