include/asm/sysreg.h

21  *	[15-12] : CRn
29 #define CRn_shift	12
245 #define SYS_PMSIDR_EL1_MAXSIZE_SHIFT	12
341 #define SYS_VBAR_EL1			sys_reg(3, 0, 12, 0, 0)
342 #define SYS_DISR_EL1			sys_reg(3, 0, 12, 1, 1)
344 #define SYS_ICC_IAR0_EL1		sys_reg(3, 0, 12, 8, 0)
345 #define SYS_ICC_EOIR0_EL1		sys_reg(3, 0, 12, 8, 1)
346 #define SYS_ICC_HPPIR0_EL1		sys_reg(3, 0, 12, 8, 2)
347 #define SYS_ICC_BPR0_EL1		sys_reg(3, 0, 12, 8, 3)
348 #define SYS_ICC_AP0Rn_EL1(n)		sys_reg(3, 0, 12, 8, 4 | n)
353 #define SYS_ICC_AP1Rn_EL1(n)		sys_reg(3, 0, 12, 9, n)
358 #define SYS_ICC_DIR_EL1			sys_reg(3, 0, 12, 11, 1)
359 #define SYS_ICC_RPR_EL1			sys_reg(3, 0, 12, 11, 3)
360 #define SYS_ICC_SGI1R_EL1		sys_reg(3, 0, 12, 11, 5)
361 #define SYS_ICC_ASGI1R_EL1		sys_reg(3, 0, 12, 11, 6)
362 #define SYS_ICC_SGI0R_EL1		sys_reg(3, 0, 12, 11, 7)
363 #define SYS_ICC_IAR1_EL1		sys_reg(3, 0, 12, 12, 0)
364 #define SYS_ICC_EOIR1_EL1		sys_reg(3, 0, 12, 12, 1)
365 #define SYS_ICC_HPPIR1_EL1		sys_reg(3, 0, 12, 12, 2)
366 #define SYS_ICC_BPR1_EL1		sys_reg(3, 0, 12, 12, 3)
367 #define SYS_ICC_CTLR_EL1		sys_reg(3, 0, 12, 12, 4)
368 #define SYS_ICC_SRE_EL1			sys_reg(3, 0, 12, 12, 5)
369 #define SYS_ICC_IGRPEN0_EL1		sys_reg(3, 0, 12, 12, 6)
370 #define SYS_ICC_IGRPEN1_EL1		sys_reg(3, 0, 12, 12, 7)
392 #define SYS_PMCR_EL0			sys_reg(3, 3, 9, 12, 0)
393 #define SYS_PMCNTENSET_EL0		sys_reg(3, 3, 9, 12, 1)
394 #define SYS_PMCNTENCLR_EL0		sys_reg(3, 3, 9, 12, 2)
395 #define SYS_PMOVSCLR_EL0		sys_reg(3, 3, 9, 12, 3)
396 #define SYS_PMSWINC_EL0			sys_reg(3, 3, 9, 12, 4)
397 #define SYS_PMSELR_EL0			sys_reg(3, 3, 9, 12, 5)
398 #define SYS_PMCEID0_EL0			sys_reg(3, 3, 9, 12, 6)
399 #define SYS_PMCEID1_EL0			sys_reg(3, 3, 9, 12, 7)
438 #define SYS_AMEVCNTR1_EL0(n)		SYS_AM_EL0(12 + ((n) >> 3), (n) & 7)
479 #define SYS_VDISR_EL2			sys_reg(3, 4, 12, 1,  1)
480 #define __SYS__AP0Rx_EL2(x)		sys_reg(3, 4, 12, 8, x)
486 #define __SYS__AP1Rx_EL2(x)		sys_reg(3, 4, 12, 9, x)
492 #define SYS_ICH_VSEIR_EL2		sys_reg(3, 4, 12, 9, 4)
493 #define SYS_ICC_SRE_EL2			sys_reg(3, 4, 12, 9, 5)
494 #define SYS_ICH_HCR_EL2			sys_reg(3, 4, 12, 11, 0)
495 #define SYS_ICH_VTR_EL2			sys_reg(3, 4, 12, 11, 1)
496 #define SYS_ICH_MISR_EL2		sys_reg(3, 4, 12, 11, 2)
497 #define SYS_ICH_EISR_EL2		sys_reg(3, 4, 12, 11, 3)
498 #define SYS_ICH_ELRSR_EL2		sys_reg(3, 4, 12, 11, 5)
499 #define SYS_ICH_VMCR_EL2		sys_reg(3, 4, 12, 11, 7)
501 #define __SYS__LR0_EL2(x)		sys_reg(3, 4, 12, 12, x)
511 #define __SYS__LR8_EL2(x)		sys_reg(3, 4, 12, 13, x)
537 #define SYS_VBAR_EL12			sys_reg(3, 5, 12, 0, 0)
565 #define SCTLR_ELx_I	(BIT(12))
650 #define ID_AA64ISAR0_SHA2_SHIFT		12
668 #define ID_AA64ISAR1_JSCVT_SHIFT	12
702 #define ID_AA64PFR0_EL3_SHIFT		12
721 #define ID_AA64PFR1_RASFRAC_SHIFT	12
768 #define ID_AA64MMFR0_SNSMEM_SHIFT	12
795 #define ID_AA64MMFR1_HPD_SHIFT		12
815 #define ID_AA64MMFR2_IESB_SHIFT		12
825 #define ID_AA64DFR0_BRPS_SHIFT		12
844 #define ID_ISAR4_SMC_SHIFT		12
854 #define ID_ISAR0_CMPBRANCH_SHIFT	12
861 #define ID_ISAR5_SHA2_SHIFT		12
869 #define ID_ISAR6_SB_SHIFT		12
878 #define ID_MMFR0_SHARELVL_SHIFT		12
887 #define ID_MMFR4_CNP_SHIFT		12
896 #define ID_PFR0_STATE3_SHIFT		12
904 #define ID_DFR0_COPTRC_SHIFT		12
916 #define MVFR0_FPTRAP_SHIFT		12
925 #define MVFR1_SIMDINT_SHIFT		12
934 #define ID_PFR1_VIRTUALIZATION_SHIFT	12
997 	.irp	num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
1017 "	.irp	num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n" \