include/asm/kvm_arm.h

1 /* SPDX-License-Identifier: GPL-2.0-only */
3  * Copyright (C) 2012,2013 - ARM Ltd
125  * We configure the Stage-2 page tables to always restrict the IPA space to be
144  *	-----------------------------------------
146  *	------------------------------------------
147  *	| Level: 0		|  2   |   -     |
148  *	------------------------------------------
150  *	------------------------------------------
152  *	------------------------------------------
153  *	| Level: 3		|  -   |   0     |
154  *	------------------------------------------
158  *	SL0(PAGE_SIZE, Entry_level) = TGRAN_SL0_BASE - Entry_Level
165  * Entry_Level = 4 - Number_of_levels.
186 	((VTCR_EL2_TGRAN_SL0_BASE - (4 - (levels))) << VTCR_EL2_SL0_SHIFT)
188 	((sl0) + 4 - VTCR_EL2_TGRAN_SL0_BASE)
193 #define VTCR_EL2_IPA(vtcr)		(64 - ((vtcr) & VTCR_EL2_T0SZ_MASK))
196  * ARM VMSAv8-64 defines an algorithm for finding the translation table
212  *    x = Magic_N - T0SZ
217  *	--------------------------------------------
219  *	--------------------------------------------
220  *	| Level: 0 (4 levels)	| 28   |  -  |  -  |
221  *	--------------------------------------------
223  *	--------------------------------------------
225  *	--------------------------------------------
226  *	| Level: 3 (1 level)	| -    | 53  | 51  |
227  *	--------------------------------------------
231  *  Magic_N(PAGE_SIZE, Level) = 64 - ((PAGE_SHIFT - 3) * Number_of_levels)
233  * where Number_of_levels = (4 - Level). We are only interested in the
236  * So, given that T0SZ = (64 - IPA_SHIFT), we can compute 'x' as follows:
238  *	x = (64 - ((PAGE_SHIFT - 3) * Number_of_levels)) - (64 - IPA_SHIFT)
239  *	  = IPA_SHIFT - ((PAGE_SHIFT - 3) * Number of levels)
245  * Since, we can resolve (PAGE_SHIFT - 3) bits at each level, and another
248  *  Bits_Entry_level = IPA_SHIFT - ((PAGE_SHIFT - 3) * (n - 1) + PAGE_SHIFT)
249  *		     = IPA_SHIFT - (PAGE_SHIFT - 3) * n - 3
253  *    = IPA_SHIFT - (PAGE_SHIFT - 3) * n
256  * levels for a given IPA size (which we do, see stage2_pt_levels())
258 #define ARM64_VTTBR_X(ipa, levels)	((ipa) - ((levels) * (PAGE_SHIFT - 3)))  argument
262 #define VTTBR_VMID_MASK(size) (_AT(u64, (1 << size) - 1) << VTTBR_VMID_SHIFT)
292 /* For compatibility with fault code shared with 32-bit */
311  *	PAR	[PA_Shift - 1	: 12] = PA	[PA_Shift - 1 : 12]
312  *	HPFAR	[PA_Shift - 9	: 4]  = FIPA	[PA_Shift - 1 : 12]
315 	(((par) & GENMASK_ULL(PHYS_MASK_SHIFT - 1, 12)) >> 8)