include/asm/cacheflush.h

1 /* SPDX-License-Identifier: GPL-2.0-only */
5  * Copyright (C) 1999-2002 Russell King.
26  *	Start addresses are inclusive and end addresses are exclusive; start
27  *	addresses should be rounded down, end addresses up.
29  *	See Documentation/core-api/cachetlb.rst for more information. Please note that
30  *	the implementation assumes non-aliasing VIPT D-cache and (aliasing)
31  *	VIPT I-cache.
38  *	flush_icache_range(start, end)
40  *		Ensure coherency between the I-cache and the D-cache in the
41  *		region described by start, end.
42  *		- start  - virtual start address
43  *		- end    - virtual end address
45  *	invalidate_icache_range(start, end)
47  *		Invalidate the I-cache in the region described by start, end.
48  *		- start  - virtual start address
49  *		- end    - virtual end address
51  *	__flush_cache_user_range(start, end)
53  *		Ensure coherency between the I-cache and the D-cache in the
54  *		region described by start, end.
55  *		- start  - virtual start address
56  *		- end    - virtual end address
61  *		- kaddr  - page address
62  *		- size   - region size
64 extern void __flush_icache_range(unsigned long start, unsigned long end);
65 extern int  invalidate_icache_range(unsigned long start, unsigned long end);
71 extern long __flush_cache_user_range(unsigned long start, unsigned long end);
74 static inline void flush_icache_range(unsigned long start, unsigned long end)  in flush_icache_range()  argument
76 	__flush_icache_range(start, end);  in flush_icache_range()
88 	 * turns out, KGDB uses IPIs to round-up the secondary CPUs during  in flush_icache_range()
90 	 * In which case, add a KGDB-specific bodge and return early.  in flush_icache_range()
117  * cache page at virtual address page->virtual.
144 #include <asm-generic/cacheflush.h>