Lines Matching +full:rk3288 +full:- +full:dw +full:- +full:mshc
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3368-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/soc/rockchip,boot-mode.h>
12 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
39 #address-cells = <0x2>;
40 #size-cells = <0x0>;
42 cpu-map {
76 compatible = "arm,cortex-a53";
78 enable-method = "psci";
79 #cooling-cells = <2>; /* min followed by max */
84 compatible = "arm,cortex-a53";
86 enable-method = "psci";
87 #cooling-cells = <2>; /* min followed by max */
92 compatible = "arm,cortex-a53";
94 enable-method = "psci";
95 #cooling-cells = <2>; /* min followed by max */
100 compatible = "arm,cortex-a53";
102 enable-method = "psci";
103 #cooling-cells = <2>; /* min followed by max */
108 compatible = "arm,cortex-a53";
110 enable-method = "psci";
111 #cooling-cells = <2>; /* min followed by max */
116 compatible = "arm,cortex-a53";
118 enable-method = "psci";
119 #cooling-cells = <2>; /* min followed by max */
124 compatible = "arm,cortex-a53";
126 enable-method = "psci";
127 #cooling-cells = <2>; /* min followed by max */
132 compatible = "arm,cortex-a53";
134 enable-method = "psci";
135 #cooling-cells = <2>; /* min followed by max */
140 compatible = "simple-bus";
141 #address-cells = <2>;
142 #size-cells = <2>;
145 dmac_peri: dma-controller@ff250000 {
150 #dma-cells = <1>;
151 arm,pl330-broken-no-flushp;
152 arm,pl330-periph-burst;
154 clock-names = "apb_pclk";
157 dmac_bus: dma-controller@ff600000 {
162 #dma-cells = <1>;
163 arm,pl330-broken-no-flushp;
164 arm,pl330-periph-burst;
166 clock-names = "apb_pclk";
170 arm-pmu {
171 compatible = "arm,armv8-pmuv3";
180 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
186 compatible = "arm,psci-0.2";
191 compatible = "arm,armv8-timer";
203 compatible = "fixed-clock";
204 clock-frequency = <24000000>;
205 clock-output-names = "xin24m";
206 #clock-cells = <0>;
210 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
212 max-frequency = <150000000>;
215 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
216 fifo-depth = <0x100>;
219 reset-names = "reset";
224 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
226 max-frequency = <150000000>;
229 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
230 fifo-depth = <0x100>;
233 reset-names = "reset";
238 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
240 max-frequency = <150000000>;
243 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
244 fifo-depth = <0x100>;
247 reset-names = "reset";
255 #io-channel-cells = <1>;
257 clock-names = "saradc", "apb_pclk";
259 reset-names = "saradc-apb";
264 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
267 clock-names = "spiclk", "apb_pclk";
269 pinctrl-names = "default";
270 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
271 #address-cells = <1>;
272 #size-cells = <0>;
277 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
280 clock-names = "spiclk", "apb_pclk";
282 pinctrl-names = "default";
283 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
284 #address-cells = <1>;
285 #size-cells = <0>;
290 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
293 clock-names = "spiclk", "apb_pclk";
295 pinctrl-names = "default";
296 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
297 #address-cells = <1>;
298 #size-cells = <0>;
303 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
306 #address-cells = <1>;
307 #size-cells = <0>;
308 clock-names = "i2c";
310 pinctrl-names = "default";
311 pinctrl-0 = <&i2c2_xfer>;
316 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
319 #address-cells = <1>;
320 #size-cells = <0>;
321 clock-names = "i2c";
323 pinctrl-names = "default";
324 pinctrl-0 = <&i2c3_xfer>;
329 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
332 #address-cells = <1>;
333 #size-cells = <0>;
334 clock-names = "i2c";
336 pinctrl-names = "default";
337 pinctrl-0 = <&i2c4_xfer>;
342 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
345 #address-cells = <1>;
346 #size-cells = <0>;
347 clock-names = "i2c";
349 pinctrl-names = "default";
350 pinctrl-0 = <&i2c5_xfer>;
355 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
357 clock-frequency = <24000000>;
359 clock-names = "baudclk", "apb_pclk";
361 reg-shift = <2>;
362 reg-io-width = <4>;
367 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
369 clock-frequency = <24000000>;
371 clock-names = "baudclk", "apb_pclk";
373 reg-shift = <2>;
374 reg-io-width = <4>;
379 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
381 clock-frequency = <24000000>;
383 clock-names = "baudclk", "apb_pclk";
385 reg-shift = <2>;
386 reg-io-width = <4>;
391 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
393 clock-frequency = <24000000>;
395 clock-names = "baudclk", "apb_pclk";
397 reg-shift = <2>;
398 reg-io-width = <4>;
402 thermal-zones {
404 polling-delay-passive = <100>; /* milliseconds */
405 polling-delay = <5000>; /* milliseconds */
407 thermal-sensors = <&tsadc 0>;
427 cooling-maps {
430 cooling-device =
438 cooling-device =
448 polling-delay-passive = <100>; /* milliseconds */
449 polling-delay = <5000>; /* milliseconds */
451 thermal-sensors = <&tsadc 1>;
466 cooling-maps {
469 cooling-device =
480 compatible = "rockchip,rk3368-tsadc";
484 clock-names = "tsadc", "apb_pclk";
486 reset-names = "tsadc-apb";
487 pinctrl-names = "init", "default", "sleep";
488 pinctrl-0 = <&otp_pin>;
489 pinctrl-1 = <&otp_out>;
490 pinctrl-2 = <&otp_pin>;
491 #thermal-sensor-cells = <1>;
492 rockchip,hw-tshut-temp = <95000>;
497 compatible = "rockchip,rk3368-gmac";
500 interrupt-names = "macirq";
506 clock-names = "stmmaceth",
514 compatible = "generic-ehci";
522 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
527 clock-names = "otg";
529 g-np-tx-fifo-size = <16>;
530 g-rx-fifo-size = <275>;
531 g-tx-fifo-size = <256 128 128 64 64 32>;
536 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
539 clock-names = "i2c";
541 pinctrl-names = "default";
542 pinctrl-0 = <&i2c0_xfer>;
543 #address-cells = <1>;
544 #size-cells = <0>;
549 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
552 #address-cells = <1>;
553 #size-cells = <0>;
554 clock-names = "i2c";
556 pinctrl-names = "default";
557 pinctrl-0 = <&i2c1_xfer>;
562 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
564 #pwm-cells = <3>;
565 pinctrl-names = "default";
566 pinctrl-0 = <&pwm0_pin>;
568 clock-names = "pwm";
573 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
575 #pwm-cells = <3>;
576 pinctrl-names = "default";
577 pinctrl-0 = <&pwm1_pin>;
579 clock-names = "pwm";
584 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
586 #pwm-cells = <3>;
588 clock-names = "pwm";
593 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
595 #pwm-cells = <3>;
596 pinctrl-names = "default";
597 pinctrl-0 = <&pwm3_pin>;
599 clock-names = "pwm";
604 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
607 clock-names = "baudclk", "apb_pclk";
609 pinctrl-names = "default";
610 pinctrl-0 = <&uart2_xfer>;
611 reg-shift = <2>;
612 reg-io-width = <4>;
617 compatible = "rockchip,rk3368-mailbox";
624 clock-names = "pclk_mailbox";
625 #mbox-cells = <1>;
630 compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
633 pmu_io_domains: io-domains {
634 compatible = "rockchip,rk3368-pmu-io-voltage-domain";
638 reboot-mode {
639 compatible = "syscon-reboot-mode";
641 mode-normal = <BOOT_NORMAL>;
642 mode-recovery = <BOOT_RECOVERY>;
643 mode-bootloader = <BOOT_FASTBOOT>;
644 mode-loader = <BOOT_BL_DOWNLOAD>;
648 cru: clock-controller@ff760000 {
649 compatible = "rockchip,rk3368-cru";
652 #clock-cells = <1>;
653 #reset-cells = <1>;
657 compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
660 io_domains: io-domains {
661 compatible = "rockchip,rk3368-io-voltage-domain";
667 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
675 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
681 compatible = "rockchip,rk3368-spdif";
685 clock-names = "mclk", "hclk";
687 dma-names = "tx";
688 pinctrl-names = "default";
689 pinctrl-0 = <&spdif_tx>;
693 i2s_2ch: i2s-2ch@ff890000 {
694 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
697 clock-names = "i2s_clk", "i2s_hclk";
700 dma-names = "tx", "rx";
704 i2s_8ch: i2s-8ch@ff898000 {
705 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
708 clock-names = "i2s_clk", "i2s_hclk";
711 dma-names = "tx", "rx";
712 pinctrl-names = "default";
713 pinctrl-0 = <&i2s_8ch_bus>;
721 interrupt-names = "iep_mmu";
723 clock-names = "aclk", "iface";
724 #iommu-cells = <0>;
733 interrupt-names = "isp_mmu";
735 clock-names = "aclk", "iface";
736 #iommu-cells = <0>;
737 rockchip,disable-mmu-reset;
745 interrupt-names = "vop_mmu";
747 clock-names = "aclk", "iface";
748 #iommu-cells = <0>;
757 interrupt-names = "hevc_mmu";
759 clock-names = "aclk", "iface";
760 #iommu-cells = <0>;
769 interrupt-names = "vepu_mmu", "vdpu_mmu";
771 clock-names = "aclk", "iface";
772 #iommu-cells = <0>;
777 compatible = "rockchip,rk3368-efuse";
779 #address-cells = <1>;
780 #size-cells = <1>;
782 clock-names = "pclk_efuse";
784 cpu_leakage: cpu-leakage@17 {
787 temp_adjust: temp-adjust@1f {
792 gic: interrupt-controller@ffb71000 {
793 compatible = "arm,gic-400";
794 interrupt-controller;
795 #interrupt-cells = <3>;
796 #address-cells = <0>;
807 compatible = "rockchip,rk3368-pinctrl";
810 #address-cells = <0x2>;
811 #size-cells = <0x2>;
815 compatible = "rockchip,gpio-bank";
820 gpio-controller;
821 #gpio-cells = <0x2>;
823 interrupt-controller;
824 #interrupt-cells = <0x2>;
828 compatible = "rockchip,gpio-bank";
833 gpio-controller;
834 #gpio-cells = <0x2>;
836 interrupt-controller;
837 #interrupt-cells = <0x2>;
841 compatible = "rockchip,gpio-bank";
846 gpio-controller;
847 #gpio-cells = <0x2>;
849 interrupt-controller;
850 #interrupt-cells = <0x2>;
854 compatible = "rockchip,gpio-bank";
859 gpio-controller;
860 #gpio-cells = <0x2>;
862 interrupt-controller;
863 #interrupt-cells = <0x2>;
866 pcfg_pull_up: pcfg-pull-up {
867 bias-pull-up;
870 pcfg_pull_down: pcfg-pull-down {
871 bias-pull-down;
874 pcfg_pull_none: pcfg-pull-none {
875 bias-disable;
878 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
879 bias-disable;
880 drive-strength = <12>;
884 emmc_clk: emmc-clk {
888 emmc_cmd: emmc-cmd {
892 emmc_pwr: emmc-pwr {
896 emmc_bus1: emmc-bus1 {
900 emmc_bus4: emmc-bus4 {
907 emmc_bus8: emmc-bus8 {
920 rgmii_pins: rgmii-pins {
938 rmii_pins: rmii-pins {
953 i2c0_xfer: i2c0-xfer {
960 i2c1_xfer: i2c1-xfer {
967 i2c2_xfer: i2c2-xfer {
974 i2c3_xfer: i2c3-xfer {
981 i2c4_xfer: i2c4-xfer {
988 i2c5_xfer: i2c5-xfer {
995 i2s_8ch_bus: i2s-8ch-bus {
1009 pwm0_pin: pwm0-pin {
1015 pwm1_pin: pwm1-pin {
1021 pwm3_pin: pwm3-pin {
1027 sdio0_bus1: sdio0-bus1 {
1031 sdio0_bus4: sdio0-bus4 {
1038 sdio0_cmd: sdio0-cmd {
1042 sdio0_clk: sdio0-clk {
1046 sdio0_cd: sdio0-cd {
1050 sdio0_wp: sdio0-wp {
1054 sdio0_pwr: sdio0-pwr {
1058 sdio0_bkpwr: sdio0-bkpwr {
1062 sdio0_int: sdio0-int {
1068 sdmmc_clk: sdmmc-clk {
1072 sdmmc_cmd: sdmmc-cmd {
1076 sdmmc_cd: sdmmc-cd {
1080 sdmmc_bus1: sdmmc-bus1 {
1084 sdmmc_bus4: sdmmc-bus4 {
1093 spdif_tx: spdif-tx {
1099 spi0_clk: spi0-clk {
1102 spi0_cs0: spi0-cs0 {
1105 spi0_cs1: spi0-cs1 {
1108 spi0_tx: spi0-tx {
1111 spi0_rx: spi0-rx {
1117 spi1_clk: spi1-clk {
1120 spi1_cs0: spi1-cs0 {
1123 spi1_cs1: spi1-cs1 {
1126 spi1_rx: spi1-rx {
1129 spi1_tx: spi1-tx {
1135 spi2_clk: spi2-clk {
1138 spi2_cs0: spi2-cs0 {
1141 spi2_rx: spi2-rx {
1144 spi2_tx: spi2-tx {
1150 otp_pin: otp-pin {
1154 otp_out: otp-out {
1160 uart0_xfer: uart0-xfer {
1165 uart0_cts: uart0-cts {
1169 uart0_rts: uart0-rts {
1175 uart1_xfer: uart1-xfer {
1180 uart1_cts: uart1-cts {
1184 uart1_rts: uart1-rts {
1190 uart2_xfer: uart2-xfer {
1198 uart3_xfer: uart3-xfer {
1203 uart3_cts: uart3-cts {
1207 uart3_rts: uart3-rts {
1213 uart4_xfer: uart4-xfer {
1218 uart4_cts: uart4-cts {
1222 uart4_rts: uart4-rts {