Lines Matching +full:phy +full:- +full:qcom +full:- +full:qusb2
1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-ipq8074.h>
11 compatible = "qcom,ipq8074";
15 compatible = "fixed-clock";
16 clock-frequency = <32000>;
17 #clock-cells = <0>;
21 compatible = "fixed-clock";
22 clock-frequency = <19200000>;
23 #clock-cells = <0>;
28 #address-cells = <0x1>;
29 #size-cells = <0x0>;
33 compatible = "arm,cortex-a53";
35 next-level-cache = <&L2_0>;
36 enable-method = "psci";
41 compatible = "arm,cortex-a53";
42 enable-method = "psci";
44 next-level-cache = <&L2_0>;
49 compatible = "arm,cortex-a53";
50 enable-method = "psci";
52 next-level-cache = <&L2_0>;
57 compatible = "arm,cortex-a53";
58 enable-method = "psci";
60 next-level-cache = <&L2_0>;
63 L2_0: l2-cache {
65 cache-level = <0x2>;
70 compatible = "arm,cortex-a53-pmu";
75 compatible = "arm,psci-1.0";
80 #address-cells = <0x1>;
81 #size-cells = <0x1>;
83 compatible = "simple-bus";
85 ssphy_1: phy@58000 {
86 compatible = "qcom,ipq8074-qmp-usb3-phy";
88 #clock-cells = <1>;
89 #address-cells = <1>;
90 #size-cells = <1>;
96 clock-names = "aux", "cfg_ahb", "ref";
100 reset-names = "phy","common";
108 #phy-cells = <0>;
110 clock-names = "pipe0";
111 clock-output-names = "gcc_usb1_pipe_clk_src";
115 qusb_phy_1: phy@59000 {
116 compatible = "qcom,ipq8074-qusb2-phy";
118 #phy-cells = <0>;
122 clock-names = "cfg_ahb", "ref";
128 ssphy_0: phy@78000 {
129 compatible = "qcom,ipq8074-qmp-usb3-phy";
131 #clock-cells = <1>;
132 #address-cells = <1>;
133 #size-cells = <1>;
139 clock-names = "aux", "cfg_ahb", "ref";
143 reset-names = "phy","common";
151 #phy-cells = <0>;
153 clock-names = "pipe0";
154 clock-output-names = "gcc_usb0_pipe_clk_src";
158 qusb_phy_0: phy@79000 {
159 compatible = "qcom,ipq8074-qusb2-phy";
161 #phy-cells = <0>;
165 clock-names = "cfg_ahb", "ref";
170 pcie_phy0: phy@86000 {
171 compatible = "qcom,ipq8074-qmp-pcie-phy";
173 #phy-cells = <0>;
175 clock-names = "pipe_clk";
176 clock-output-names = "pcie20_phy0_pipe_clk";
180 reset-names = "phy",
185 pcie_phy1: phy@8e000 {
186 compatible = "qcom,ipq8074-qmp-pcie-phy";
188 #phy-cells = <0>;
190 clock-names = "pipe_clk";
191 clock-output-names = "pcie20_phy1_pipe_clk";
195 reset-names = "phy",
201 compatible = "qcom,ipq8074-pinctrl";
204 gpio-controller;
205 gpio-ranges = <&tlmm 0 0 70>;
206 #gpio-cells = <0x2>;
207 interrupt-controller;
208 #interrupt-cells = <0x2>;
210 serial_4_pins: serial4-pinmux {
213 drive-strength = <8>;
214 bias-disable;
217 i2c_0_pins: i2c-0-pinmux {
220 drive-strength = <8>;
221 bias-disable;
224 spi_0_pins: spi-0-pins {
227 drive-strength = <8>;
228 bias-disable;
231 hsuart_pins: hsuart-pins {
234 drive-strength = <8>;
235 bias-disable;
238 qpic_pins: qpic-pins {
245 drive-strength = <8>;
246 bias-disable;
251 compatible = "qcom,gcc-ipq8074";
253 #clock-cells = <0x1>;
254 #reset-cells = <0x1>;
258 compatible = "qcom,sdhci-msm-v4";
260 reg-names = "hc_mem", "core_mem";
264 interrupt-names = "hc_irq", "pwr_irq";
269 clock-names = "xo", "iface", "core";
270 max-frequency = <384000000>;
271 mmc-ddr-1_8v;
272 mmc-hs200-1_8v;
273 mmc-hs400-1_8v;
274 bus-width = <8>;
280 compatible = "qcom,bam-v1.7.0";
284 clock-names = "bam_clk";
285 #dma-cells = <1>;
286 qcom,ee = <0>;
290 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
295 clock-names = "core", "iface";
300 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
305 clock-names = "core", "iface";
308 dma-names = "tx", "rx";
309 pinctrl-0 = <&hsuart_pins>;
310 pinctrl-names = "default";
315 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
320 clock-names = "core", "iface";
321 pinctrl-0 = <&serial_4_pins>;
322 pinctrl-names = "default";
327 compatible = "qcom,spi-qup-v2.2.1";
328 #address-cells = <1>;
329 #size-cells = <0>;
332 spi-max-frequency = <50000000>;
335 clock-names = "core", "iface";
337 dma-names = "tx", "rx";
338 pinctrl-0 = <&spi_0_pins>;
339 pinctrl-names = "default";
344 compatible = "qcom,i2c-qup-v2.2.1";
345 #address-cells = <1>;
346 #size-cells = <0>;
351 clock-names = "iface", "core";
352 clock-frequency = <400000>;
354 dma-names = "rx", "tx";
355 pinctrl-0 = <&i2c_0_pins>;
356 pinctrl-names = "default";
361 compatible = "qcom,i2c-qup-v2.2.1";
362 #address-cells = <1>;
363 #size-cells = <0>;
368 clock-names = "iface", "core";
369 clock-frequency = <100000>;
371 dma-names = "rx", "tx";
376 compatible = "qcom,bam-v1.7.0";
380 clock-names = "bam_clk";
381 #dma-cells = <1>;
382 qcom,ee = <0>;
387 compatible = "qcom,ipq8074-nand";
389 #address-cells = <1>;
390 #size-cells = <0>;
393 clock-names = "core", "aon";
398 dma-names = "tx", "rx", "cmd";
399 pinctrl-0 = <&qpic_pins>;
400 pinctrl-names = "default";
405 compatible = "qcom,dwc3";
407 #address-cells = <1>;
408 #size-cells = <1>;
415 clock-names = "sys_noc_axi",
420 assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
423 assigned-clock-rates = <133330000>,
435 phy-names = "usb2-phy", "usb3-phy";
436 tx-fifo-resize;
437 snps,is-utmi-l1-suspend;
438 snps,hird-threshold = /bits/ 8 <0x0>;
446 compatible = "qcom,dwc3";
448 #address-cells = <1>;
449 #size-cells = <1>;
456 clock-names = "sys_noc_axi",
461 assigned-clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
464 assigned-clock-rates = <133330000>,
476 phy-names = "usb2-phy", "usb3-phy";
477 tx-fifo-resize;
478 snps,is-utmi-l1-suspend;
479 snps,hird-threshold = /bits/ 8 <0x0>;
486 intc: interrupt-controller@b000000 {
487 compatible = "qcom,msm-qgic2";
488 interrupt-controller;
489 #interrupt-cells = <0x3>;
494 compatible = "arm,armv8-timer";
502 compatible = "qcom,kpss-wdt";
506 timeout-sec = <30>;
510 #address-cells = <1>;
511 #size-cells = <1>;
513 compatible = "arm,armv7-timer-mem";
515 clock-frequency = <19200000>;
518 frame-number = <0>;
526 frame-number = <1>;
533 frame-number = <2>;
540 frame-number = <3>;
547 frame-number = <4>;
554 frame-number = <5>;
561 frame-number = <6>;
569 compatible = "qcom,pcie-ipq8074";
574 reg-names = "dbi", "elbi", "parf", "config";
576 linux,pci-domain = <1>;
577 bus-range = <0x00 0xff>;
578 num-lanes = <1>;
579 #address-cells = <3>;
580 #size-cells = <2>;
583 phy-names = "pciephy";
588 0 0xd00000>; /* non-prefetchable memory */
591 interrupt-names = "msi";
592 #interrupt-cells = <1>;
593 interrupt-map-mask = <0 0 0 0x7>;
594 interrupt-map = <0 0 0 1 &intc 0 142
608 clock-names = "iface",
620 reset-names = "pipe",
631 compatible = "qcom,pcie-ipq8074";
636 reg-names = "dbi", "elbi", "parf", "config";
638 linux,pci-domain = <0>;
639 bus-range = <0x00 0xff>;
640 num-lanes = <1>;
641 #address-cells = <3>;
642 #size-cells = <2>;
645 phy-names = "pciephy";
650 0 0xd00000>; /* non-prefetchable memory */
653 interrupt-names = "msi";
654 #interrupt-cells = <1>;
655 interrupt-map-mask = <0 0 0 0x7>;
656 interrupt-map = <0 0 0 1 &intc 0 75
671 clock-names = "iface",
683 reset-names = "pipe",