Lines Matching +full:dma +full:- +full:safe +full:- +full:map
1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra194-clock.h>
3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
7 #include <dt-bindings/power/tegra194-powergate.h>
8 #include <dt-bindings/reset/tegra194-reset.h>
9 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
10 #include <dt-bindings/memory/tegra194-mc.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
20 compatible = "simple-bus";
21 #address-cells = <1>;
22 #size-cells = <1>;
26 compatible = "nvidia,tegra194-misc";
32 compatible = "nvidia,tegra194-gpio";
33 reg-names = "security", "gpio";
42 #interrupt-cells = <2>;
43 interrupt-controller;
44 #gpio-cells = <2>;
45 gpio-controller;
49 compatible = "nvidia,tegra194-eqos",
50 "nvidia,tegra186-eqos",
51 "snps,dwc-qos-ethernet-4.10";
59 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
61 reset-names = "eqos";
64 interconnect-names = "dma-mem", "write";
67 snps,write-requests = <1>;
68 snps,read-requests = <3>;
69 snps,burst-map = <0x7>;
75 compatible = "nvidia,tegra194-aconnect",
76 "nvidia,tegra210-aconnect";
79 clock-names = "ape", "apb2ape";
80 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>;
81 #address-cells = <1>;
82 #size-cells = <1>;
86 adma: dma-controller@2930000 {
87 compatible = "nvidia,tegra194-adma",
88 "nvidia,tegra186-adma";
90 interrupt-parent = <&agic>;
123 #dma-cells = <1>;
125 clock-names = "d_audio";
129 agic: interrupt-controller@2a40000 {
130 compatible = "nvidia,tegra194-agic",
131 "nvidia,tegra210-agic";
132 #interrupt-cells = <3>;
133 interrupt-controller;
140 clock-names = "clk";
145 compatible = "nvidia,tegra194-ahub",
146 "nvidia,tegra186-ahub";
149 clock-names = "ahub";
150 assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>;
151 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
152 #address-cells = <1>;
153 #size-cells = <1>;
158 compatible = "nvidia,tegra194-admaif",
159 "nvidia,tegra186-admaif";
181 dma-names = "rx1", "tx1",
205 compatible = "nvidia,tegra194-i2s",
206 "nvidia,tegra210-i2s";
210 clock-names = "i2s", "sync_input";
211 assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>;
212 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
213 assigned-clock-rates = <1536000>;
214 sound-name-prefix = "I2S1";
219 compatible = "nvidia,tegra194-i2s",
220 "nvidia,tegra210-i2s";
224 clock-names = "i2s", "sync_input";
225 assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>;
226 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
227 assigned-clock-rates = <1536000>;
228 sound-name-prefix = "I2S2";
233 compatible = "nvidia,tegra194-i2s",
234 "nvidia,tegra210-i2s";
238 clock-names = "i2s", "sync_input";
239 assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>;
240 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
241 assigned-clock-rates = <1536000>;
242 sound-name-prefix = "I2S3";
247 compatible = "nvidia,tegra194-i2s",
248 "nvidia,tegra210-i2s";
252 clock-names = "i2s", "sync_input";
253 assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>;
254 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
255 assigned-clock-rates = <1536000>;
256 sound-name-prefix = "I2S4";
261 compatible = "nvidia,tegra194-i2s",
262 "nvidia,tegra210-i2s";
266 clock-names = "i2s", "sync_input";
267 assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>;
268 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
269 assigned-clock-rates = <1536000>;
270 sound-name-prefix = "I2S5";
275 compatible = "nvidia,tegra194-i2s",
276 "nvidia,tegra210-i2s";
280 clock-names = "i2s", "sync_input";
281 assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>;
282 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
283 assigned-clock-rates = <1536000>;
284 sound-name-prefix = "I2S6";
289 compatible = "nvidia,tegra194-dmic",
290 "nvidia,tegra210-dmic";
293 clock-names = "dmic";
294 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>;
295 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
296 assigned-clock-rates = <3072000>;
297 sound-name-prefix = "DMIC1";
302 compatible = "nvidia,tegra194-dmic",
303 "nvidia,tegra210-dmic";
306 clock-names = "dmic";
307 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>;
308 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
309 assigned-clock-rates = <3072000>;
310 sound-name-prefix = "DMIC2";
315 compatible = "nvidia,tegra194-dmic",
316 "nvidia,tegra210-dmic";
319 clock-names = "dmic";
320 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>;
321 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
322 assigned-clock-rates = <3072000>;
323 sound-name-prefix = "DMIC3";
328 compatible = "nvidia,tegra194-dmic",
329 "nvidia,tegra210-dmic";
332 clock-names = "dmic";
333 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>;
334 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
335 assigned-clock-rates = <3072000>;
336 sound-name-prefix = "DMIC4";
341 compatible = "nvidia,tegra194-dspk",
342 "nvidia,tegra186-dspk";
345 clock-names = "dspk";
346 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>;
347 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
348 assigned-clock-rates = <12288000>;
349 sound-name-prefix = "DSPK1";
354 compatible = "nvidia,tegra194-dspk",
355 "nvidia,tegra186-dspk";
358 clock-names = "dspk";
359 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>;
360 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
361 assigned-clock-rates = <12288000>;
362 sound-name-prefix = "DSPK2";
369 compatible = "nvidia,tegra194-pinmux";
380 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
381 nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
392 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
393 nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
400 mc: memory-controller@2c00000 {
401 compatible = "nvidia,tegra194-mc";
406 #interconnect-cells = <1>;
409 #address-cells = <2>;
410 #size-cells = <2>;
429 * Limit the DMA range for memory clients to [38:0].
431 dma-ranges = <0x0 0x0 0x0 0x80 0x0>;
433 emc: external-memory-controller@2c60000 {
434 compatible = "nvidia,tegra194-emc";
438 clock-names = "emc";
440 #interconnect-cells = <0>;
447 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
449 reg-shift = <2>;
452 clock-names = "serial";
454 reset-names = "serial";
459 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
461 reg-shift = <2>;
464 clock-names = "serial";
466 reset-names = "serial";
471 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
473 reg-shift = <2>;
476 clock-names = "serial";
478 reset-names = "serial";
483 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
485 reg-shift = <2>;
488 clock-names = "serial";
490 reset-names = "serial";
495 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
497 reg-shift = <2>;
500 clock-names = "serial";
502 reset-names = "serial";
507 compatible = "nvidia,tegra194-i2c";
510 #address-cells = <1>;
511 #size-cells = <0>;
513 clock-names = "div-clk";
515 reset-names = "i2c";
520 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
522 reg-shift = <2>;
525 clock-names = "serial";
527 reset-names = "serial";
532 compatible = "nvidia,tegra194-i2c";
535 #address-cells = <1>;
536 #size-cells = <0>;
538 clock-names = "div-clk";
540 reset-names = "i2c";
546 compatible = "nvidia,tegra194-i2c";
549 #address-cells = <1>;
550 #size-cells = <0>;
552 clock-names = "div-clk";
554 reset-names = "i2c";
555 pinctrl-0 = <&state_dpaux1_i2c>;
556 pinctrl-1 = <&state_dpaux1_off>;
557 pinctrl-names = "default", "idle";
563 compatible = "nvidia,tegra194-i2c";
566 #address-cells = <1>;
567 #size-cells = <0>;
569 clock-names = "div-clk";
571 reset-names = "i2c";
572 pinctrl-0 = <&state_dpaux0_i2c>;
573 pinctrl-1 = <&state_dpaux0_off>;
574 pinctrl-names = "default", "idle";
580 compatible = "nvidia,tegra194-i2c";
583 #address-cells = <1>;
584 #size-cells = <0>;
586 clock-names = "div-clk";
588 reset-names = "i2c";
589 pinctrl-0 = <&state_dpaux2_i2c>;
590 pinctrl-1 = <&state_dpaux2_off>;
591 pinctrl-names = "default", "idle";
597 compatible = "nvidia,tegra194-i2c";
600 #address-cells = <1>;
601 #size-cells = <0>;
603 clock-names = "div-clk";
605 reset-names = "i2c";
606 pinctrl-0 = <&state_dpaux3_i2c>;
607 pinctrl-1 = <&state_dpaux3_off>;
608 pinctrl-names = "default", "idle";
613 compatible = "nvidia,tegra194-pwm",
614 "nvidia,tegra186-pwm";
617 clock-names = "pwm";
619 reset-names = "pwm";
621 #pwm-cells = <2>;
625 compatible = "nvidia,tegra194-pwm",
626 "nvidia,tegra186-pwm";
629 clock-names = "pwm";
631 reset-names = "pwm";
633 #pwm-cells = <2>;
637 compatible = "nvidia,tegra194-pwm",
638 "nvidia,tegra186-pwm";
641 clock-names = "pwm";
643 reset-names = "pwm";
645 #pwm-cells = <2>;
649 compatible = "nvidia,tegra194-pwm",
650 "nvidia,tegra186-pwm";
653 clock-names = "pwm";
655 reset-names = "pwm";
657 #pwm-cells = <2>;
661 compatible = "nvidia,tegra194-pwm",
662 "nvidia,tegra186-pwm";
665 clock-names = "pwm";
667 reset-names = "pwm";
669 #pwm-cells = <2>;
673 compatible = "nvidia,tegra194-pwm",
674 "nvidia,tegra186-pwm";
677 clock-names = "pwm";
679 reset-names = "pwm";
681 #pwm-cells = <2>;
685 compatible = "nvidia,tegra194-pwm",
686 "nvidia,tegra186-pwm";
689 clock-names = "pwm";
691 reset-names = "pwm";
693 #pwm-cells = <2>;
697 compatible = "nvidia,tegra194-sdhci";
702 clock-names = "sdhci", "tmclk";
704 reset-names = "sdhci";
707 interconnect-names = "dma-mem", "write";
708 nvidia,pad-autocal-pull-up-offset-3v3-timeout =
710 nvidia,pad-autocal-pull-down-offset-3v3-timeout =
712 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
713 nvidia,pad-autocal-pull-down-offset-1v8-timeout =
715 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
716 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
717 nvidia,default-tap = <0x9>;
718 nvidia,default-trim = <0x5>;
723 compatible = "nvidia,tegra194-sdhci";
728 clock-names = "sdhci", "tmclk";
730 reset-names = "sdhci";
733 interconnect-names = "dma-mem", "write";
734 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
735 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
736 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
737 nvidia,pad-autocal-pull-down-offset-3v3-timeout =
739 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
740 nvidia,pad-autocal-pull-down-offset-1v8-timeout =
742 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
743 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
744 nvidia,default-tap = <0x9>;
745 nvidia,default-trim = <0x5>;
750 compatible = "nvidia,tegra194-sdhci";
755 clock-names = "sdhci", "tmclk";
756 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>,
758 assigned-clock-parents =
761 reset-names = "sdhci";
764 interconnect-names = "dma-mem", "write";
765 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
766 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
767 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
768 nvidia,pad-autocal-pull-down-offset-1v8-timeout =
770 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
771 nvidia,pad-autocal-pull-down-offset-3v3-timeout =
773 nvidia,default-tap = <0x8>;
774 nvidia,default-trim = <0x14>;
775 nvidia,dqs-trim = <40>;
776 supports-cqe;
781 compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda";
787 clock-names = "hda", "hda2codec_2x", "hda2hdmi";
791 reset-names = "hda", "hda2codec_2x", "hda2hdmi";
792 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
795 interconnect-names = "dma-mem", "write";
800 compatible = "nvidia,tegra194-xusb-padctl";
803 reg-names = "padctl", "ao";
806 reset-names = "padctl";
813 clock-names = "trk";
816 usb2-0 {
819 #phy-cells = <0>;
822 usb2-1 {
825 #phy-cells = <0>;
828 usb2-2 {
831 #phy-cells = <0>;
834 usb2-3 {
837 #phy-cells = <0>;
844 usb3-0 {
847 #phy-cells = <0>;
850 usb3-1 {
853 #phy-cells = <0>;
856 usb3-2 {
859 #phy-cells = <0>;
862 usb3-3 {
865 #phy-cells = <0>;
872 usb2-0 {
876 usb2-1 {
880 usb2-2 {
884 usb2-3 {
888 usb3-0 {
892 usb3-1 {
896 usb3-2 {
900 usb3-3 {
907 compatible = "nvidia,tegra194-xudc";
910 reg-names = "base", "fpci";
916 clock-names = "dev", "ss", "ss_src", "fs_src";
917 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>,
919 power-domain-names = "dev", "ss";
920 nvidia,xusb-padctl = <&xusb_padctl>;
925 compatible = "nvidia,tegra194-xusb";
928 reg-names = "hcd", "fpci";
942 clock-names = "xusb_host", "xusb_falcon_src",
947 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>,
949 power-domain-names = "xusb_host", "xusb_ss";
951 nvidia,xusb-padctl = <&xusb_padctl>;
956 compatible = "nvidia,tegra194-efuse";
959 clock-names = "fuse";
962 gic: interrupt-controller@3881000 {
963 compatible = "arm,gic-400";
964 #interrupt-cells = <3>;
965 interrupt-controller;
972 interrupt-parent = <&gic>;
976 compatible = "nvidia,tegra194-cec";
980 clock-names = "cec";
985 compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp";
996 interrupt-names = "doorbell", "shared0", "shared1", "shared2",
999 #mbox-cells = <2>;
1003 compatible = "nvidia,tegra194-p2u";
1005 reg-names = "ctl";
1007 #phy-cells = <0>;
1011 compatible = "nvidia,tegra194-p2u";
1013 reg-names = "ctl";
1015 #phy-cells = <0>;
1019 compatible = "nvidia,tegra194-p2u";
1021 reg-names = "ctl";
1023 #phy-cells = <0>;
1027 compatible = "nvidia,tegra194-p2u";
1029 reg-names = "ctl";
1031 #phy-cells = <0>;
1035 compatible = "nvidia,tegra194-p2u";
1037 reg-names = "ctl";
1039 #phy-cells = <0>;
1043 compatible = "nvidia,tegra194-p2u";
1045 reg-names = "ctl";
1047 #phy-cells = <0>;
1051 compatible = "nvidia,tegra194-p2u";
1053 reg-names = "ctl";
1055 #phy-cells = <0>;
1059 compatible = "nvidia,tegra194-p2u";
1061 reg-names = "ctl";
1063 #phy-cells = <0>;
1067 compatible = "nvidia,tegra194-p2u";
1069 reg-names = "ctl";
1071 #phy-cells = <0>;
1075 compatible = "nvidia,tegra194-p2u";
1077 reg-names = "ctl";
1079 #phy-cells = <0>;
1083 compatible = "nvidia,tegra194-p2u";
1085 reg-names = "ctl";
1087 #phy-cells = <0>;
1091 compatible = "nvidia,tegra194-p2u";
1093 reg-names = "ctl";
1095 #phy-cells = <0>;
1099 compatible = "nvidia,tegra194-p2u";
1101 reg-names = "ctl";
1103 #phy-cells = <0>;
1107 compatible = "nvidia,tegra194-p2u";
1109 reg-names = "ctl";
1111 #phy-cells = <0>;
1115 compatible = "nvidia,tegra194-p2u";
1117 reg-names = "ctl";
1119 #phy-cells = <0>;
1123 compatible = "nvidia,tegra194-p2u";
1125 reg-names = "ctl";
1127 #phy-cells = <0>;
1131 compatible = "nvidia,tegra194-p2u";
1133 reg-names = "ctl";
1135 #phy-cells = <0>;
1139 compatible = "nvidia,tegra194-p2u";
1141 reg-names = "ctl";
1143 #phy-cells = <0>;
1147 compatible = "nvidia,tegra194-p2u";
1149 reg-names = "ctl";
1151 #phy-cells = <0>;
1155 compatible = "nvidia,tegra194-p2u";
1157 reg-names = "ctl";
1159 #phy-cells = <0>;
1163 compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp";
1173 interrupt-names = "shared1", "shared2", "shared3", "shared4";
1174 #mbox-cells = <2>;
1178 compatible = "nvidia,tegra194-i2c";
1181 #address-cells = <1>;
1182 #size-cells = <0>;
1184 clock-names = "div-clk";
1186 reset-names = "i2c";
1191 compatible = "nvidia,tegra194-i2c";
1194 #address-cells = <1>;
1195 #size-cells = <0>;
1197 clock-names = "div-clk";
1199 reset-names = "i2c";
1204 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
1206 reg-shift = <2>;
1209 clock-names = "serial";
1211 reset-names = "serial";
1216 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
1218 reg-shift = <2>;
1221 clock-names = "serial";
1223 reset-names = "serial";
1228 compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc";
1230 interrupt-parent = <&pmc>;
1233 clock-names = "rtc";
1238 compatible = "nvidia,tegra194-gpio-aon";
1239 reg-names = "security", "gpio";
1243 gpio-controller;
1244 #gpio-cells = <2>;
1245 interrupt-controller;
1246 #interrupt-cells = <2>;
1250 compatible = "nvidia,tegra194-pwm",
1251 "nvidia,tegra186-pwm";
1254 clock-names = "pwm";
1256 reset-names = "pwm";
1258 #pwm-cells = <2>;
1262 compatible = "nvidia,tegra194-pmc";
1268 reg-names = "pmc", "wake", "aotag", "scratch", "misc";
1270 #interrupt-cells = <2>;
1271 interrupt-controller;
1275 compatible = "nvidia,tegra194-host1x";
1278 reg-names = "hypervisor", "vm";
1281 interrupt-names = "syncpt", "host1x";
1283 clock-names = "host1x";
1285 reset-names = "host1x";
1287 #address-cells = <1>;
1288 #size-cells = <1>;
1292 interconnect-names = "dma-mem";
1294 display-hub@15200000 {
1295 compatible = "nvidia,tegra194-display";
1304 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
1308 clock-names = "disp", "hub";
1311 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1313 #address-cells = <1>;
1314 #size-cells = <1>;
1319 compatible = "nvidia,tegra194-dc";
1323 clock-names = "dc";
1325 reset-names = "dc";
1327 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1330 interconnect-names = "dma-mem", "read-1";
1337 compatible = "nvidia,tegra194-dc";
1341 clock-names = "dc";
1343 reset-names = "dc";
1345 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>;
1348 interconnect-names = "dma-mem", "read-1";
1355 compatible = "nvidia,tegra194-dc";
1359 clock-names = "dc";
1361 reset-names = "dc";
1363 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
1366 interconnect-names = "dma-mem", "read-1";
1373 compatible = "nvidia,tegra194-dc";
1377 clock-names = "dc";
1379 reset-names = "dc";
1381 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
1384 interconnect-names = "dma-mem", "read-1";
1392 compatible = "nvidia,tegra194-vic";
1396 clock-names = "vic";
1398 reset-names = "vic";
1400 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>;
1403 interconnect-names = "dma-mem", "write";
1407 compatible = "nvidia,tegra194-dpaux";
1412 clock-names = "dpaux", "parent";
1414 reset-names = "dpaux";
1417 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1419 state_dpaux0_aux: pinmux-aux {
1420 groups = "dpaux-io";
1424 state_dpaux0_i2c: pinmux-i2c {
1425 groups = "dpaux-io";
1429 state_dpaux0_off: pinmux-off {
1430 groups = "dpaux-io";
1434 i2c-bus {
1435 #address-cells = <1>;
1436 #size-cells = <0>;
1441 compatible = "nvidia,tegra194-dpaux";
1446 clock-names = "dpaux", "parent";
1448 reset-names = "dpaux";
1451 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1453 state_dpaux1_aux: pinmux-aux {
1454 groups = "dpaux-io";
1458 state_dpaux1_i2c: pinmux-i2c {
1459 groups = "dpaux-io";
1463 state_dpaux1_off: pinmux-off {
1464 groups = "dpaux-io";
1468 i2c-bus {
1469 #address-cells = <1>;
1470 #size-cells = <0>;
1475 compatible = "nvidia,tegra194-dpaux";
1480 clock-names = "dpaux", "parent";
1482 reset-names = "dpaux";
1485 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1487 state_dpaux2_aux: pinmux-aux {
1488 groups = "dpaux-io";
1492 state_dpaux2_i2c: pinmux-i2c {
1493 groups = "dpaux-io";
1497 state_dpaux2_off: pinmux-off {
1498 groups = "dpaux-io";
1502 i2c-bus {
1503 #address-cells = <1>;
1504 #size-cells = <0>;
1509 compatible = "nvidia,tegra194-dpaux";
1514 clock-names = "dpaux", "parent";
1516 reset-names = "dpaux";
1519 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1521 state_dpaux3_aux: pinmux-aux {
1522 groups = "dpaux-io";
1526 state_dpaux3_i2c: pinmux-i2c {
1527 groups = "dpaux-io";
1531 state_dpaux3_off: pinmux-off {
1532 groups = "dpaux-io";
1536 i2c-bus {
1537 #address-cells = <1>;
1538 #size-cells = <0>;
1543 compatible = "nvidia,tegra194-sor";
1552 clock-names = "sor", "out", "parent", "dp", "safe",
1555 reset-names = "sor";
1556 pinctrl-0 = <&state_dpaux0_aux>;
1557 pinctrl-1 = <&state_dpaux0_i2c>;
1558 pinctrl-2 = <&state_dpaux0_off>;
1559 pinctrl-names = "aux", "i2c", "off";
1562 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1567 compatible = "nvidia,tegra194-sor";
1576 clock-names = "sor", "out", "parent", "dp", "safe",
1579 reset-names = "sor";
1580 pinctrl-0 = <&state_dpaux1_aux>;
1581 pinctrl-1 = <&state_dpaux1_i2c>;
1582 pinctrl-2 = <&state_dpaux1_off>;
1583 pinctrl-names = "aux", "i2c", "off";
1586 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1591 compatible = "nvidia,tegra194-sor";
1600 clock-names = "sor", "out", "parent", "dp", "safe",
1603 reset-names = "sor";
1604 pinctrl-0 = <&state_dpaux2_aux>;
1605 pinctrl-1 = <&state_dpaux2_i2c>;
1606 pinctrl-2 = <&state_dpaux2_off>;
1607 pinctrl-names = "aux", "i2c", "off";
1610 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1615 compatible = "nvidia,tegra194-sor";
1624 clock-names = "sor", "out", "parent", "dp", "safe",
1627 reset-names = "sor";
1628 pinctrl-0 = <&state_dpaux3_aux>;
1629 pinctrl-1 = <&state_dpaux3_i2c>;
1630 pinctrl-2 = <&state_dpaux3_off>;
1631 pinctrl-names = "aux", "i2c", "off";
1634 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1645 interrupt-names = "stall", "nonstall";
1649 clock-names = "gpu", "pwr", "fuse";
1651 reset-names = "gpu";
1652 dma-coherent;
1654 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>;
1667 interconnect-names = "dma-mem", "read-0-hp", "write-0",
1668 "read-1", "read-1-hp", "write-1",
1669 "read-2", "read-2-hp", "write-2",
1670 "read-3", "read-3-hp", "write-3";
1675 compatible = "nvidia,tegra194-pcie";
1676 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
1681 reg-names = "appl", "config", "atu_dma", "dbi";
1685 #address-cells = <3>;
1686 #size-cells = <2>;
1688 num-lanes = <1>;
1689 num-viewport = <8>;
1690 linux,pci-domain = <1>;
1693 clock-names = "core";
1697 reset-names = "apb", "core";
1701 interrupt-names = "intr", "msi";
1703 #interrupt-cells = <1>;
1704 interrupt-map-mask = <0 0 0 0>;
1705 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1709 nvidia,aspm-cmrt-us = <60>;
1710 nvidia,aspm-pwr-on-t-us = <20>;
1711 nvidia,aspm-l0s-entrance-latency-us = <3>;
1713 bus-range = <0x0 0xff>;
1716 …00000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 Ki…
1721 interconnect-names = "read", "write";
1725 compatible = "nvidia,tegra194-pcie";
1726 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
1731 reg-names = "appl", "config", "atu_dma", "dbi";
1735 #address-cells = <3>;
1736 #size-cells = <2>;
1738 num-lanes = <1>;
1739 num-viewport = <8>;
1740 linux,pci-domain = <2>;
1743 clock-names = "core";
1747 reset-names = "apb", "core";
1751 interrupt-names = "intr", "msi";
1753 #interrupt-cells = <1>;
1754 interrupt-map-mask = <0 0 0 0>;
1755 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1759 nvidia,aspm-cmrt-us = <60>;
1760 nvidia,aspm-pwr-on-t-us = <20>;
1761 nvidia,aspm-l0s-entrance-latency-us = <3>;
1763 bus-range = <0x0 0xff>;
1766 …00000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 Ki…
1771 interconnect-names = "read", "write";
1775 compatible = "nvidia,tegra194-pcie";
1776 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
1781 reg-names = "appl", "config", "atu_dma", "dbi";
1785 #address-cells = <3>;
1786 #size-cells = <2>;
1788 num-lanes = <1>;
1789 num-viewport = <8>;
1790 linux,pci-domain = <3>;
1793 clock-names = "core";
1797 reset-names = "apb", "core";
1801 interrupt-names = "intr", "msi";
1803 #interrupt-cells = <1>;
1804 interrupt-map-mask = <0 0 0 0>;
1805 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1809 nvidia,aspm-cmrt-us = <60>;
1810 nvidia,aspm-pwr-on-t-us = <20>;
1811 nvidia,aspm-l0s-entrance-latency-us = <3>;
1813 bus-range = <0x0 0xff>;
1816 …<0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB +…
1821 interconnect-names = "read", "write";
1825 compatible = "nvidia,tegra194-pcie";
1826 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
1831 reg-names = "appl", "config", "atu_dma", "dbi";
1835 #address-cells = <3>;
1836 #size-cells = <2>;
1838 num-lanes = <4>;
1839 num-viewport = <8>;
1840 linux,pci-domain = <4>;
1843 clock-names = "core";
1847 reset-names = "apb", "core";
1851 interrupt-names = "intr", "msi";
1853 #interrupt-cells = <1>;
1854 interrupt-map-mask = <0 0 0 0>;
1855 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1859 nvidia,aspm-cmrt-us = <60>;
1860 nvidia,aspm-pwr-on-t-us = <20>;
1861 nvidia,aspm-l0s-entrance-latency-us = <3>;
1863 bus-range = <0x0 0xff>;
1866 …000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB…
1871 interconnect-names = "read", "write";
1875 compatible = "nvidia,tegra194-pcie";
1876 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
1881 reg-names = "appl", "config", "atu_dma", "dbi";
1885 #address-cells = <3>;
1886 #size-cells = <2>;
1888 num-lanes = <8>;
1889 num-viewport = <8>;
1890 linux,pci-domain = <0>;
1893 clock-names = "core";
1897 reset-names = "apb", "core";
1901 interrupt-names = "intr", "msi";
1903 #interrupt-cells = <1>;
1904 interrupt-map-mask = <0 0 0 0>;
1905 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1909 nvidia,aspm-cmrt-us = <60>;
1910 nvidia,aspm-pwr-on-t-us = <20>;
1911 nvidia,aspm-l0s-entrance-latency-us = <3>;
1913 bus-range = <0x0 0xff>;
1916 …000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB…
1921 interconnect-names = "read", "write";
1925 compatible = "nvidia,tegra194-pcie";
1926 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
1931 reg-names = "appl", "config", "atu_dma", "dbi";
1935 #address-cells = <3>;
1936 #size-cells = <2>;
1938 num-lanes = <8>;
1939 num-viewport = <8>;
1940 linux,pci-domain = <5>;
1942 pinctrl-names = "default";
1943 pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;
1947 clock-names = "core", "core_m";
1951 reset-names = "apb", "core";
1955 interrupt-names = "intr", "msi";
1959 #interrupt-cells = <1>;
1960 interrupt-map-mask = <0 0 0 0>;
1961 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1963 nvidia,aspm-cmrt-us = <60>;
1964 nvidia,aspm-pwr-on-t-us = <20>;
1965 nvidia,aspm-l0s-entrance-latency-us = <3>;
1967 bus-range = <0x0 0xff>;
1970 …000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB…
1975 interconnect-names = "read", "write";
1979 compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
1980 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
1985 reg-names = "appl", "atu_dma", "dbi", "addr_space";
1989 num-lanes = <4>;
1990 num-ib-windows = <2>;
1991 num-ob-windows = <8>;
1994 clock-names = "core";
1998 reset-names = "apb", "core";
2001 interrupt-names = "intr";
2005 nvidia,aspm-cmrt-us = <60>;
2006 nvidia,aspm-pwr-on-t-us = <20>;
2007 nvidia,aspm-l0s-entrance-latency-us = <3>;
2011 compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
2012 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
2017 reg-names = "appl", "atu_dma", "dbi", "addr_space";
2021 num-lanes = <8>;
2022 num-ib-windows = <2>;
2023 num-ob-windows = <8>;
2026 clock-names = "core";
2030 reset-names = "apb", "core";
2033 interrupt-names = "intr";
2037 nvidia,aspm-cmrt-us = <60>;
2038 nvidia,aspm-pwr-on-t-us = <20>;
2039 nvidia,aspm-l0s-entrance-latency-us = <3>;
2043 compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
2044 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
2049 reg-names = "appl", "atu_dma", "dbi", "addr_space";
2053 num-lanes = <8>;
2054 num-ib-windows = <2>;
2055 num-ob-windows = <8>;
2057 pinctrl-names = "default";
2058 pinctrl-0 = <&clkreq_c5_bi_dir_state>;
2061 clock-names = "core";
2065 reset-names = "apb", "core";
2068 interrupt-names = "intr";
2072 nvidia,aspm-cmrt-us = <60>;
2073 nvidia,aspm-pwr-on-t-us = <20>;
2074 nvidia,aspm-l0s-entrance-latency-us = <3>;
2078 compatible = "nvidia,tegra194-sysram", "mmio-sram";
2080 #address-cells = <1>;
2081 #size-cells = <1>;
2086 label = "cpu-bpmp-tx";
2092 label = "cpu-bpmp-rx";
2098 compatible = "nvidia,tegra186-bpmp";
2102 #clock-cells = <1>;
2103 #reset-cells = <1>;
2104 #power-domain-cells = <1>;
2109 interconnect-names = "read", "write", "dma-mem", "dma-write";
2112 compatible = "nvidia,tegra186-bpmp-i2c";
2113 nvidia,bpmp-bus-id = <5>;
2114 #address-cells = <1>;
2115 #size-cells = <0>;
2119 compatible = "nvidia,tegra186-bpmp-thermal";
2120 #thermal-sensor-cells = <1>;
2125 compatible = "nvidia,tegra194-ccplex";
2127 #address-cells = <1>;
2128 #size-cells = <0>;
2131 compatible = "nvidia,tegra194-carmel";
2134 enable-method = "psci";
2135 i-cache-size = <131072>;
2136 i-cache-line-size = <64>;
2137 i-cache-sets = <512>;
2138 d-cache-size = <65536>;
2139 d-cache-line-size = <64>;
2140 d-cache-sets = <256>;
2141 next-level-cache = <&l2c_0>;
2145 compatible = "nvidia,tegra194-carmel";
2148 enable-method = "psci";
2149 i-cache-size = <131072>;
2150 i-cache-line-size = <64>;
2151 i-cache-sets = <512>;
2152 d-cache-size = <65536>;
2153 d-cache-line-size = <64>;
2154 d-cache-sets = <256>;
2155 next-level-cache = <&l2c_0>;
2159 compatible = "nvidia,tegra194-carmel";
2162 enable-method = "psci";
2163 i-cache-size = <131072>;
2164 i-cache-line-size = <64>;
2165 i-cache-sets = <512>;
2166 d-cache-size = <65536>;
2167 d-cache-line-size = <64>;
2168 d-cache-sets = <256>;
2169 next-level-cache = <&l2c_1>;
2173 compatible = "nvidia,tegra194-carmel";
2176 enable-method = "psci";
2177 i-cache-size = <131072>;
2178 i-cache-line-size = <64>;
2179 i-cache-sets = <512>;
2180 d-cache-size = <65536>;
2181 d-cache-line-size = <64>;
2182 d-cache-sets = <256>;
2183 next-level-cache = <&l2c_1>;
2187 compatible = "nvidia,tegra194-carmel";
2190 enable-method = "psci";
2191 i-cache-size = <131072>;
2192 i-cache-line-size = <64>;
2193 i-cache-sets = <512>;
2194 d-cache-size = <65536>;
2195 d-cache-line-size = <64>;
2196 d-cache-sets = <256>;
2197 next-level-cache = <&l2c_2>;
2201 compatible = "nvidia,tegra194-carmel";
2204 enable-method = "psci";
2205 i-cache-size = <131072>;
2206 i-cache-line-size = <64>;
2207 i-cache-sets = <512>;
2208 d-cache-size = <65536>;
2209 d-cache-line-size = <64>;
2210 d-cache-sets = <256>;
2211 next-level-cache = <&l2c_2>;
2215 compatible = "nvidia,tegra194-carmel";
2218 enable-method = "psci";
2219 i-cache-size = <131072>;
2220 i-cache-line-size = <64>;
2221 i-cache-sets = <512>;
2222 d-cache-size = <65536>;
2223 d-cache-line-size = <64>;
2224 d-cache-sets = <256>;
2225 next-level-cache = <&l2c_3>;
2229 compatible = "nvidia,tegra194-carmel";
2232 enable-method = "psci";
2233 i-cache-size = <131072>;
2234 i-cache-line-size = <64>;
2235 i-cache-sets = <512>;
2236 d-cache-size = <65536>;
2237 d-cache-line-size = <64>;
2238 d-cache-sets = <256>;
2239 next-level-cache = <&l2c_3>;
2242 cpu-map {
2284 l2c_0: l2-cache0 {
2285 cache-size = <2097152>;
2286 cache-line-size = <64>;
2287 cache-sets = <2048>;
2288 next-level-cache = <&l3c>;
2291 l2c_1: l2-cache1 {
2292 cache-size = <2097152>;
2293 cache-line-size = <64>;
2294 cache-sets = <2048>;
2295 next-level-cache = <&l3c>;
2298 l2c_2: l2-cache2 {
2299 cache-size = <2097152>;
2300 cache-line-size = <64>;
2301 cache-sets = <2048>;
2302 next-level-cache = <&l3c>;
2305 l2c_3: l2-cache3 {
2306 cache-size = <2097152>;
2307 cache-line-size = <64>;
2308 cache-sets = <2048>;
2309 next-level-cache = <&l3c>;
2312 l3c: l3-cache {
2313 cache-size = <4194304>;
2314 cache-line-size = <64>;
2315 cache-sets = <4096>;
2320 compatible = "arm,psci-1.0";
2326 compatible = "nvidia,tegra194-tcu";
2329 mbox-names = "rx", "tx";
2332 thermal-zones {
2334 thermal-sensors = <&{/bpmp/thermal}
2340 thermal-sensors = <&{/bpmp/thermal}
2346 thermal-sensors = <&{/bpmp/thermal}
2352 thermal-sensors = <&{/bpmp/thermal}
2358 thermal-sensors = <&{/bpmp/thermal}
2364 thermal-sensors = <&{/bpmp/thermal}
2371 compatible = "arm,armv8-timer";
2380 interrupt-parent = <&gic>;
2381 always-on;