Lines Matching +full:psci +full:- +full:0
1 // SPDX-License-Identifier: GPL-2.0
7 #include <dt-bindings/clock/mt6797-clk.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/pinctrl/mt6797-pinfunc.h>
14 interrupt-parent = <&sysirq>;
15 #address-cells = <2>;
16 #size-cells = <2>;
18 psci {
19 compatible = "arm,psci-0.2";
24 #address-cells = <1>;
25 #size-cells = <0>;
27 cpu0: cpu@0 {
29 compatible = "arm,cortex-a53";
30 enable-method = "psci";
31 reg = <0x000>;
36 compatible = "arm,cortex-a53";
37 enable-method = "psci";
38 reg = <0x001>;
43 compatible = "arm,cortex-a53";
44 enable-method = "psci";
45 reg = <0x002>;
50 compatible = "arm,cortex-a53";
51 enable-method = "psci";
52 reg = <0x003>;
57 compatible = "arm,cortex-a53";
58 enable-method = "psci";
59 reg = <0x100>;
64 compatible = "arm,cortex-a53";
65 enable-method = "psci";
66 reg = <0x101>;
71 compatible = "arm,cortex-a53";
72 enable-method = "psci";
73 reg = <0x102>;
78 compatible = "arm,cortex-a53";
79 enable-method = "psci";
80 reg = <0x103>;
85 compatible = "arm,cortex-a72";
86 enable-method = "psci";
87 reg = <0x200>;
92 compatible = "arm,cortex-a72";
93 enable-method = "psci";
94 reg = <0x201>;
98 clk26m: oscillator@0 {
99 compatible = "fixed-clock";
100 #clock-cells = <0>;
101 clock-frequency = <26000000>;
102 clock-output-names = "clk26m";
106 compatible = "arm,armv8-timer";
107 interrupt-parent = <&gic>;
115 compatible = "mediatek,mt6797-topckgen";
116 reg = <0 0x10000000 0 0x1000>;
117 #clock-cells = <1>;
121 compatible = "mediatek,mt6797-infracfg", "syscon";
122 reg = <0 0x10001000 0 0x1000>;
123 #clock-cells = <1>;
127 compatible = "mediatek,mt6797-pinctrl";
128 reg = <0 0x10005000 0 0x1000>,
129 <0 0x10002000 0 0x400>,
130 <0 0x10002400 0 0x400>,
131 <0 0x10002800 0 0x400>,
132 <0 0x10002C00 0 0x400>;
133 reg-names = "gpio", "iocfgl", "iocfgb",
135 gpio-controller;
136 #gpio-cells = <2>;
209 scpsys: power-controller@10006000 {
210 compatible = "mediatek,mt6797-scpsys";
211 #power-domain-cells = <1>;
212 reg = <0 0x10006000 0 0x1000>;
216 clock-names = "mfg", "mm", "vdec";
221 compatible = "mediatek,mt6797-wdt", "mediatek,mt6589-wdt";
222 reg = <0 0x10007000 0 0x100>;
226 compatible = "mediatek,mt6797-apmixedsys";
227 reg = <0 0x1000c000 0 0x1000>;
228 #clock-cells = <1>;
231 sysirq: intpol-controller@10200620 {
232 compatible = "mediatek,mt6797-sysirq",
233 "mediatek,mt6577-sysirq";
234 interrupt-controller;
235 #interrupt-cells = <3>;
236 interrupt-parent = <&gic>;
237 reg = <0 0x10220620 0 0x20>,
238 <0 0x10220690 0 0x10>;
242 compatible = "mediatek,mt6797-uart",
243 "mediatek,mt6577-uart";
244 reg = <0 0x11002000 0 0x400>;
248 clock-names = "baud", "bus";
253 compatible = "mediatek,mt6797-uart",
254 "mediatek,mt6577-uart";
255 reg = <0 0x11003000 0 0x400>;
259 clock-names = "baud", "bus";
264 compatible = "mediatek,mt6797-uart",
265 "mediatek,mt6577-uart";
266 reg = <0 0x11004000 0 0x400>;
270 clock-names = "baud", "bus";
275 compatible = "mediatek,mt6797-uart",
276 "mediatek,mt6577-uart";
277 reg = <0 0x11005000 0 0x400>;
281 clock-names = "baud", "bus";
286 compatible = "mediatek,mt6797-i2c",
287 "mediatek,mt6577-i2c";
288 id = <0>;
289 reg = <0 0x11007000 0 0x1000>,
290 <0 0x11000100 0 0x80>;
294 clock-names = "main", "dma";
295 clock-div = <10>;
296 #address-cells = <1>;
297 #size-cells = <0>;
302 compatible = "mediatek,mt6797-i2c",
303 "mediatek,mt6577-i2c";
305 reg = <0 0x11008000 0 0x1000>,
306 <0 0x11000180 0 0x80>;
310 clock-names = "main", "dma";
311 clock-div = <10>;
312 #address-cells = <1>;
313 #size-cells = <0>;
318 compatible = "mediatek,mt6797-i2c",
319 "mediatek,mt6577-i2c";
321 reg = <0 0x11009000 0 0x1000>,
322 <0 0x11000200 0 0x80>;
327 clock-names = "main", "dma", "arb";
328 clock-div = <10>;
329 #address-cells = <1>;
330 #size-cells = <0>;
335 compatible = "mediatek,mt6797-i2c",
336 "mediatek,mt6577-i2c";
338 reg = <0 0x1100d000 0 0x1000>,
339 <0 0x11000280 0 0x80>;
344 clock-names = "main", "dma", "arb";
345 clock-div = <10>;
346 #address-cells = <1>;
347 #size-cells = <0>;
352 compatible = "mediatek,mt6797-i2c",
353 "mediatek,mt6577-i2c";
355 reg = <0 0x1100e000 0 0x1000>,
356 <0 0x11000500 0 0x80>;
360 clock-names = "main", "dma";
361 clock-div = <10>;
362 #address-cells = <1>;
363 #size-cells = <0>;
368 compatible = "mediatek,mt6797-i2c",
369 "mediatek,mt6577-i2c";
371 reg = <0 0x11010000 0 0x1000>,
372 <0 0x11000580 0 0x80>;
376 clock-names = "main", "dma";
377 clock-div = <10>;
378 #address-cells = <1>;
379 #size-cells = <0>;
384 compatible = "mediatek,mt6797-i2c",
385 "mediatek,mt6577-i2c";
387 reg = <0 0x11011000 0 0x1000>,
388 <0 0x11000300 0 0x80>;
392 clock-names = "main", "dma";
393 clock-div = <10>;
394 #address-cells = <1>;
395 #size-cells = <0>;
400 compatible = "mediatek,mt6797-i2c",
401 "mediatek,mt6577-i2c";
403 reg = <0 0x11013000 0 0x1000>,
404 <0 0x11000400 0 0x80>;
409 clock-names = "main", "dma", "arb";
410 clock-div = <10>;
411 #address-cells = <1>;
412 #size-cells = <0>;
417 compatible = "mediatek,mt6797-i2c",
418 "mediatek,mt6577-i2c";
420 reg = <0 0x11014000 0 0x1000>,
421 <0 0x11000480 0 0x80>;
426 clock-names = "main", "dma", "arb";
427 clock-div = <10>;
428 #address-cells = <1>;
429 #size-cells = <0>;
434 compatible = "mediatek,mt6797-i2c",
435 "mediatek,mt6577-i2c";
437 reg = <0 0x1101c000 0 0x1000>,
438 <0 0x11000380 0 0x80>;
442 clock-names = "main", "dma";
443 clock-div = <10>;
444 #address-cells = <1>;
445 #size-cells = <0>;
450 compatible = "mediatek,mt6797-mmsys", "syscon";
451 reg = <0 0x14000000 0 0x1000>;
452 #clock-cells = <1>;
456 compatible = "mediatek,mt6797-imgsys", "syscon";
457 reg = <0 0x15000000 0 0x1000>;
458 #clock-cells = <1>;
462 compatible = "mediatek,mt6797-vdecsys", "syscon";
463 reg = <0 0x16000000 0 0x10000>;
464 #clock-cells = <1>;
468 compatible = "mediatek,mt6797-vencsys", "syscon";
469 reg = <0 0x17000000 0 0x1000>;
470 #clock-cells = <1>;
473 gic: interrupt-controller@19000000 {
474 compatible = "arm,gic-v3";
475 #interrupt-cells = <3>;
476 interrupt-parent = <&gic>;
478 interrupt-controller;
479 reg = <0 0x19000000 0 0x10000>, /* GICD */
480 <0 0x19200000 0 0x200000>, /* GICR */
481 <0 0x10240000 0 0x2000>; /* GICC */