dts/freescale/imx8mp-evk.dts

1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "imx8mp.dtsi"
12 	compatible = "fsl,imx8mp-evk", "fsl,imx8mp";
15 		stdout-path = &uart2;
18 	gpio-leds {
19 		compatible = "gpio-leds";
20 		pinctrl-names = "default";
21 		pinctrl-0 = <&pinctrl_gpio_led>;
26 			default-state = "on";
36 	reg_usdhc2_vmmc: regulator-usdhc2 {
37 		compatible = "regulator-fixed";
38 		pinctrl-names = "default";
39 		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
40 		regulator-name = "VSD_3V3";
41 		regulator-min-microvolt = <3300000>;
42 		regulator-max-microvolt = <3300000>;
44 		enable-active-high;
49 	pinctrl-names = "default";
50 	pinctrl-0 = <&pinctrl_fec>;
51 	phy-mode = "rgmii-id";
52 	phy-handle = <&ethphy1>;
53 	fsl,magic-packet;
57 		#address-cells = <1>;
58 		#size-cells = <0>;
60 		ethphy1: ethernet-phy@1 {
61 			compatible = "ethernet-phy-ieee802.3-c22";
63 			eee-broken-1000t;
64 			reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
70 	clock-frequency = <400000>;
71 	pinctrl-names = "default";
72 	pinctrl-0 = <&pinctrl_i2c3>;
78 		gpio-controller;
79 		#gpio-cells = <2>;
89 	pinctrl-names = "default";
90 	pinctrl-0 = <&pinctrl_uart2>;
95 	assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
96 	assigned-clock-rates = <400000000>;
97 	pinctrl-names = "default", "state_100mhz", "state_200mhz";
98 	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
99 	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
100 	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
101 	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
102 	vmmc-supply = <&reg_usdhc2_vmmc>;
103 	bus-width = <4>;
108 	assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
109 	assigned-clock-rates = <400000000>;
110 	pinctrl-names = "default", "state_100mhz", "state_200mhz";
111 	pinctrl-0 = <&pinctrl_usdhc3>;
112 	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
113 	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
114 	bus-width = <8>;
115 	non-removable;
120 	pinctrl-names = "default";
121 	pinctrl-0 = <&pinctrl_wdog>;
122 	fsl,ext-reset-output;
185 	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
197 	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
231 	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
247 	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {