Lines Matching +full:spi +full:- +full:tx +full:- +full:bus +full:- +full:width
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-1046A family SoC.
11 /dts-v1/;
13 #include "fsl-ls1046a.dtsi"
17 compatible = "fsl,ls1046a-qds", "fsl,ls1046a";
31 stdout-path = "serial0:115200n8";
36 bus-num = <0>;
40 #address-cells = <1>;
41 #size-cells = <1>;
42 compatible = "n25q128a11", "jedec,spi-nor";
44 spi-max-frequency = <10000000>;
48 #address-cells = <1>;
49 #size-cells = <1>;
50 compatible = "sst25wf040b", "jedec,spi-nor";
51 spi-cpol;
52 spi-cpha;
54 spi-max-frequency = <10000000>;
58 #address-cells = <1>;
59 #size-cells = <1>;
60 compatible = "en25s64", "jedec,spi-nor";
61 spi-cpol;
62 spi-cpha;
64 spi-max-frequency = <10000000>;
82 #address-cells = <1>;
83 #size-cells = <0>;
86 #address-cells = <1>;
87 #size-cells = <0>;
93 shunt-resistor = <1000>;
99 shunt-resistor = <1000>;
104 #address-cells = <1>;
105 #size-cells = <0>;
125 temp-sensor@4c {
134 #address-cells = <2>;
135 #size-cells = <1>;
143 compatible = "cfi-flash";
145 big-endian;
146 bank-width = <2>;
147 device-width = <1>;
151 compatible = "fsl,ifc-nand";
155 fpga: board-control@2,0 {
156 compatible = "fsl,ls1046aqds-fpga", "fsl,fpga-qixis";
170 #address-cells = <1>;
171 #size-cells = <1>;
172 spi-max-frequency = <20000000>;
173 spi-rx-bus-width = <4>;
174 spi-tx-bus-width = <4>;
179 #include "fsl-ls1046-post.dtsi"