dts/freescale/fsl-ls1043a-rdb.dts

1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3  * Device Tree Include file for Freescale Layerscape-1043A family SoC.
5  * Copyright 2014-2015 Freescale Semiconductor, Inc.
11 /dts-v1/;
12 #include "fsl-ls1043a.dtsi"
16 	compatible = "fsl,ls1043a-rdb", "fsl,ls1043a";
26 		stdout-path = "serial0:115200n8";
35 		shunt-resistor = <1000>;
57 	#address-cells = <2>;
58 	#size-cells = <1>;
65 			compatible = "cfi-flash";
66 			#address-cells = <1>;
67 			#size-cells = <1>;
69 			big-endian;
70 			bank-width = <2>;
71 			device-width = <1>;
75 			compatible = "fsl,ifc-nand";
76 			#address-cells = <1>;
77 			#size-cells = <1>;
81 		cpld: board-control@2,0 {
82 			compatible = "fsl,ls1043ardb-cpld";
88 	bus-num = <0>;
92 		#address-cells = <1>;
93 		#size-cells = <1>;
94 		compatible = "n25q128a13", "jedec,spi-nor";  /* 16MB */
96 		spi-max-frequency = <1000000>; /* input clock */
102 		spi-max-frequency = <2000000>;
103 		fsl,spi-cs-sck-delay = <100>;
104 		fsl,spi-sck-cs-delay = <50>;
110 		spi-max-frequency = <2000000>;
111 		fsl,spi-cs-sck-delay = <100>;
112 		fsl,spi-sck-cs-delay = <50>;
124 #include "fsl-ls1043-post.dtsi"
128 		phy-handle = <&qsgmii_phy1>;
129 		phy-connection-type = "qsgmii";
133 		phy-handle = <&qsgmii_phy2>;
134 		phy-connection-type = "qsgmii";
138 		phy-handle = <&rgmii_phy1>;
139 		phy-connection-type = "rgmii-id";
143 		phy-handle = <&rgmii_phy2>;
144 		phy-connection-type = "rgmii-id";
148 		phy-handle = <&qsgmii_phy3>;
149 		phy-connection-type = "qsgmii";
153 		phy-handle = <&qsgmii_phy4>;
154 		phy-connection-type = "qsgmii";
158 		phy-handle = <&aqr105_phy>;
159 		phy-connection-type = "xgmii";
163 		rgmii_phy1: ethernet-phy@1 {
167 		rgmii_phy2: ethernet-phy@2 {
171 		qsgmii_phy1: ethernet-phy@4 {
175 		qsgmii_phy2: ethernet-phy@5 {
179 		qsgmii_phy3: ethernet-phy@6 {
183 		qsgmii_phy4: ethernet-phy@7 {
189 		aqr105_phy: ethernet-phy@1 {
190 			compatible = "ethernet-phy-ieee802.3-c45";
199 		compatible = "fsl,ucc-hdlc";
200 		rx-clock-name = "clk8";
201 		tx-clock-name = "clk9";
202 		fsl,rx-sync-clock = "rsync_pin";
203 		fsl,tx-sync-clock = "tsync_pin";
204 		fsl,tx-timeslot-mask = <0xfffffffe>;
205 		fsl,rx-timeslot-mask = <0xfffffffe>;
206 		fsl,tdm-framer-type = "e1";
207 		fsl,tdm-id = <0>;
208 		fsl,siram-entry-id = <0>;
209 		fsl,tdm-interface;