Lines Matching +full:spi +full:- +full:tx +full:- +full:bus +full:- +full:width
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 /dts-v1/;
13 #include "fsl-ls1028a.dtsi"
17 compatible = "fsl,ls1028a-qds", "fsl,ls1028a";
29 stdout-path = "serial0:115200n8";
37 sys_mclk: clock-mclk {
38 compatible = "fixed-clock";
39 #clock-cells = <0>;
40 clock-frequency = <25000000>;
43 reg_1p8v: regulator-1p8v {
44 compatible = "regulator-fixed";
45 regulator-name = "1P8V";
46 regulator-min-microvolt = <1800000>;
47 regulator-max-microvolt = <1800000>;
48 regulator-always-on;
51 sb_3v3: regulator-sb3v3 {
52 compatible = "regulator-fixed";
53 regulator-name = "3v3_vbus";
54 regulator-min-microvolt = <3300000>;
55 regulator-max-microvolt = <3300000>;
56 regulator-boot-on;
57 regulator-always-on;
61 compatible = "simple-audio-card";
62 simple-audio-card,format = "i2s";
63 simple-audio-card,widgets =
68 simple-audio-card,routing =
75 simple-audio-card,cpu {
76 sound-dai = <&sai1>;
77 frame-master;
78 bitclock-master;
81 simple-audio-card,codec {
82 sound-dai = <&sgtl5000>;
83 frame-master;
84 bitclock-master;
85 system-clock-frequency = <25000000>;
89 mdio-mux {
90 compatible = "mdio-mux-multiplexer";
91 mux-controls = <&mux 0>;
92 mdio-parent-bus = <&enetc_mdio_pf3>;
93 #address-cells=<1>;
94 #size-cells = <0>;
96 /* on-board RGMII PHY */
98 #address-cells = <1>;
99 #size-cells = <0>;
102 qds_phy1: ethernet-phy@5 {
111 bus-num = <0>;
115 #address-cells = <1>;
116 #size-cells = <1>;
117 compatible = "jedec,spi-nor";
118 spi-cpol;
119 spi-cpha;
121 spi-max-frequency = <10000000>;
125 #address-cells = <1>;
126 #size-cells = <1>;
127 compatible = "jedec,spi-nor";
128 spi-cpol;
129 spi-cpha;
131 spi-max-frequency = <10000000>;
135 #address-cells = <1>;
136 #size-cells = <1>;
137 compatible = "jedec,spi-nor";
138 spi-cpol;
139 spi-cpha;
141 spi-max-frequency = <10000000>;
146 bus-num = <1>;
150 #address-cells = <1>;
151 #size-cells = <1>;
152 compatible = "jedec,spi-nor";
153 spi-cpol;
154 spi-cpha;
156 spi-max-frequency = <10000000>;
160 #address-cells = <1>;
161 #size-cells = <1>;
162 compatible = "jedec,spi-nor";
163 spi-cpol;
164 spi-cpha;
166 spi-max-frequency = <10000000>;
170 #address-cells = <1>;
171 #size-cells = <1>;
172 compatible = "jedec,spi-nor";
173 spi-cpol;
174 spi-cpha;
176 spi-max-frequency = <10000000>;
181 bus-num = <2>;
185 #address-cells = <1>;
186 #size-cells = <1>;
187 compatible = "jedec,spi-nor";
188 spi-cpol;
189 spi-cpha;
191 spi-max-frequency = <10000000>;
215 compatible = "jedec,spi-nor";
216 #address-cells = <1>;
217 #size-cells = <1>;
218 spi-max-frequency = <50000000>;
219 /* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */
220 spi-rx-bus-width = <8>; /* 8 SPI Rx lines */
221 spi-tx-bus-width = <1>; /* 1 SPI Tx line */
229 i2c-mux@77 {
232 #address-cells = <1>;
233 #size-cells = <0>;
236 #address-cells = <1>;
237 #size-cells = <0>;
240 current-monitor@40 {
243 shunt-resistor = <1000>;
246 current-monitor@41 {
249 shunt-resistor = <1000>;
254 #address-cells = <1>;
255 #size-cells = <0>;
258 temperature-sensor@4c {
261 vcc-supply = <&sb_3v3>;
281 #address-cells = <1>;
282 #size-cells = <0>;
285 sgtl5000: audio-codec@a {
286 #sound-dai-cells = <0>;
289 VDDA-supply = <®_1p8v>;
290 VDDIO-supply = <®_1p8v>;
297 compatible = "fsl,ls1028aqds-fpga", "fsl,fpga-qixis-i2c",
298 "simple-mfd";
301 mux: mux-controller {
302 compatible = "reg-mux";
303 #mux-control-cells = <1>;
304 mux-reg-masks = <0x54 0xf0>; /* 0: reg 0x54, bits 7:4 */
311 phy-handle = <&qds_phy1>;
312 phy-connection-type = "rgmii-id";