Lines Matching +full:armv8 +full:- +full:based
1 # SPDX-License-Identifier: GPL-2.0-only
161 if $(cc-option,-fpatchable-function-entry=2)
205 ARM 64-bit (AArch64) Linux support.
237 # VA_BITS - PAGE_SHIFT - 3
330 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
357 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
362 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
365 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
371 data cache clean-and-invalidate.
379 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
384 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
393 data cache clean-and-invalidate.
401 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
406 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
409 If a Cortex-A53 processor is executing a store or prefetch for
416 data cache clean-and-invalidate.
424 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
429 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
438 data cache clean-and-invalidate.
446 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
450 erratum 832075 on Cortex-A57 parts up to r1p2.
452 Affected Cortex-A57 parts might deadlock when exclusive load/store
453 instructions to Write-Back memory are mixed with Device loads.
455 The workaround is to promote device loads to use Load-Acquire
464 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
469 erratum 834220 on Cortex-A57 parts up to r1p2.
471 Affected Cortex-A57 parts might report a Stage 2 translation
485 bool "Cortex-A53: 845719: a load might read incorrect data"
490 erratum 845719 on Cortex-A53 parts up to r0p4.
492 When running a compat (AArch32) userspace on an affected Cortex-A53
498 return to a 32-bit task.
506 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
510 This option links the kernel with '--fix-cortex-a53-843419' and
513 Cortex-A53 parts up to r0p4.
518 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
521 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
523 Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect
525 without a break-before-make. The workaround is to disable the usage
532 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
536 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
539 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
549 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
553 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
555 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
562 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
566 This option adds work arounds for ARM Cortex-A57 erratum 1319537
569 Cortex-A57 and A72 cores could end-up with corrupted TLBs by
575 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
579 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
581 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
591 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
595 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
597 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
601 break-before-make sequence, then under very rare circumstances
607 bool "Cortex-A76: Software Step might prevent interrupt recognition"
610 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
612 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
625 bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
628 This option adds a workaround for ARM Neoverse-N1 erratum
631 Affected Neoverse-N1 cores could execute a stale instruction when
636 forces user-space to perform cache maintenance.
641 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read"
644 This option adds a workaround for Arm Cortex-A77 erratum 1508412.
646 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
647 of a store-exclusive or read of PAR_EL1 and a load with device or
648 non-cacheable memory attributes. The workaround depends on a firmware
666 This implements two gicv3-its errata workarounds for ThunderX. Both
702 contains data for a non-current ASID. The fix is to
713 interrupts in host. Trapping both GICv3 group-0 and group-1
736 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
739 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
740 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
744 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
745 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
746 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
747 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
750 The workaround only affects the Fujitsu-A64FX.
807 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
811 MSI doorbell writes with non-zero values for the device ID.
841 look-up. AArch32 emulation requires applications compiled
857 bool "36-bit" if EXPERT
861 bool "39-bit"
865 bool "42-bit"
869 bool "47-bit"
873 bool "48-bit"
876 bool "52-bit"
879 Enable 52-bit virtual addressing for userspace when explicitly
880 requested via a hint to mmap(). The kernel will also use 52-bit
882 this feature is available, otherwise it reverts to 48-bit).
884 NOTE: Enabling 52-bit virtual addressing in conjunction with
885 ARMv8.3 Pointer Authentication will result in the PAC being
887 impact on its susceptibility to brute-force attacks.
889 If unsure, select 48-bit virtual addressing instead.
894 bool "Force 52-bit virtual addresses for userspace"
897 For systems with 52-bit userspace VAs enabled, the kernel will attempt
898 to maintain compatibility with older software by providing 48-bit VAs
901 This configuration option disables the 48-bit compatibility logic, and
902 forces all userspace addresses to be 52-bit on HW that supports it. One
923 bool "48-bit"
926 bool "52-bit (ARMv8.2)"
930 Enable support for a 52-bit physical address space, introduced as
931 part of the ARMv8.2-LPA extension.
934 do not support ARMv8.2-LPA, but with some added memory overhead (and
953 bool "Build big-endian kernel"
955 Say Y if you plan on running a kernel with a big-endian userspace.
958 bool "Build little-endian kernel"
960 Say Y if you plan on running a kernel with a little-endian userspace.
966 bool "Multi-core scheduler support"
968 Multi-core scheduler support improves the CPU scheduler's decision
969 making when dealing with multi-core CPU chips at a cost of slightly
980 int "Maximum number of CPUs (2-4096)"
985 bool "Support for hot-pluggable CPUs"
997 Enable NUMA (Non-Uniform Memory Access) support.
1065 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1096 bool "kexec file based system call"
1100 file based and takes file descriptors as system call argument
1133 loaded in the main kernel with kexec-tools into a specially
1137 For more details see Documentation/admin-guide/kdump/kdump.rst
1169 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1178 Speculation attacks against some high-performance processors can
1190 Apply read-only attributes of VM areas to the linear alias of
1191 the backing pages as well. This prevents code or read-only data
1204 user-space memory directly by pointing TTBR0_EL1 to a reserved
1215 Documentation/arm64/tagged-address-abi.rst.
1218 bool "Kernel support for 32-bit EL0"
1225 This option enables support for a 32-bit EL0 running under a 64-bit
1226 kernel at EL1. AArch32-specific components such as system calls,
1234 If you want to execute 32-bit userspace applications, say Y.
1239 bool "Enable kuser helpers page for 32-bit applications"
1242 Warning: disabling this option may break 32-bit user programs.
1248 to ARMv8 without modification.
1266 bool "Enable vDSO for 32-bit applications"
1271 Place in the process address space of 32-bit applications an
1275 You must have a 32-bit build of glibc 2.22 or later for programs
1279 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1283 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1284 otherwise with '-marm'.
1287 bool "Emulate deprecated/obsolete ARMv8 instructions"
1303 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1326 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1327 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1342 The SETEND instruction alters the data-endianness of the
1343 AArch32 EL0, and is deprecated in ARMv8.
1350 for this feature to be enabled. If a new CPU - which doesn't support mixed
1351 endian - is hotplugged in after this feature has been enabled, there could
1359 menu "ARMv8.1 architectural features"
1365 The ARMv8.1 architecture extensions introduce support for
1370 Similarly, writes to read-only pages with the DBM bit set will
1371 clear the read-only bit (AP[2]) instead of raising a
1375 to work on pre-ARMv8.1 hardware and the performance impact is
1382 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1383 prevents the kernel or hypervisor from accessing user-space (EL0)
1395 depends on $(as-instr,.arch_extension lse)
1402 As part of the Large System Extensions, ARMv8.1 introduces new
1406 Say Y here to make use of these instructions for the in-kernel
1427 menu "ARMv8.2 architectural features"
1433 User Access Override (UAO; part of the ARMv8.2 Extensions)
1438 variant of the load/store instructions. This ensures that user-space
1443 Choosing this option will cause copy_to_user() et al to use user-space
1455 Say Y to enable support for the persistent memory API based on the
1456 ARMv8.2 DCPoP feature.
1467 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1494 menu "ARMv8.3 architectural features"
1506 Pointer authentication (part of the ARMv8.3 Extensions) provides
1514 context-switched along with the process.
1516 If the compiler supports the -mbranch-protection or
1517 -msign-return-address flag (e.g. GCC 7 or later), then this option
1538 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
1542 def_bool $(cc-option,-msign-return-address=all)
1545 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a)
1548 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
1552 menu "ARMv8.4 architectural features"
1559 by the ARMv8.4 CPU architecture. This enables support for version 1
1578 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a)
1585 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
1593 menu "ARMv8.5 architectural features"
1599 Branch Target Identification (part of the ARMv8.5 Extensions)
1607 authentication mechanism provided as part of the ARMv8.3 Extensions.
1635 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
1641 E0PD (part of the ARMv8.5 extensions) allows us to ensure
1653 Random number generation (part of the ARMv8.5 Extensions)
1659 # ".arch armv8.5-a+memtag" below. However, this was incomplete
1663 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
1671 Memory Tagging (part of the ARMv8.5 Extensions) provides
1672 architectural support for run-time, always-on detection of
1674 to eliminate vulnerabilities arising from memory-unsafe
1682 not be allowed a late bring-up.
1688 Documentation/arm64/memory-tagging-extension.rst.
1718 If you need the kernel to boot on SVE-capable hardware with broken
1751 bool "Support for NMI-like interrupts"
1754 Adds support for mimicking Non-Maskable Interrupts through the use of
1798 random u64 value in /chosen/kaslr-seed at kernel entry.
1823 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
1846 Provide a set of default command-line options at build time by
1857 command-line options your boot loader passes to the kernel.
1876 by UEFI firmware (such as non-volatile variables, realtime
1890 continue to boot on existing non-UEFI platforms.